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| features ? high performance, low power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions - most single clock cycle execution ? 32 8 general purpose working registers ? fully static operation ? up to 1 mips throughput per mhz ? on-chip 2-cycle multiplier ? data and non-volatile program memory ? 8/16kbytes of in-system programmable program memory flash ? endurance: 10,000 write/erase cycles ? lock bits protection ? optional 2/4kbytes boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? 512 bytes of in-sys tem programmable eeprom ? four bytes page size ? 256/1024 bytes internal sram ? on-chip debug support (debugwire) ? peripheral features ? one 12-bit high speed psc (power stag e controllers with extended psc2 features) ? non overlapping inverted pwm output pins with flexible dead-time ? variable pwm duty cycle and frequency ? synchronous update of all pwm registers ? enhanced resolution mode (16 bits) ? additional register for adc synchronization ? input capture ? four output pins and output matrix ? one 12-bit high speed psc (power stage controller) ? auto-stop function for event driven pfc implementation ? non overlapping inverted pwm output pins with flexible dead-time ? variable pwm duty cycle and frequency ? synchronous update of all pwm registers ? enhanced resolution mode (16 bits) ? input capture ? one 16-bit simple general purpose timer/counter ? 10-bit adc ? up to 11 single ended channels and one fully differenti al adc channel pair ? programmable gain (5, 10, 20 , 40 on differential channel) ? internal reference voltage ? one 10-bit dac ? three analog comparators with ? resistor-array to adjust comparison voltage ? dac to adjust comparison voltage ? one spi ? three external interrupts ? programmable watchdog timer wi th separate on-chip oscillator ? special microcontroller features ? low power idle, noise reduction, and power down modes 8-bit atmel microcontroller with 8/16k bytes in-system programmable flash at90pwm81 at90pwm161 7734q?avr?02/12
2 7734q?avr?02/12 at90pwm81/161 ? power-on reset and programmable brown-out detection ? flag array in bit-programmable i/o space (three bytes) ? in-system programmable via spi port ? internal low power calibrated rc oscillator (8mhz or 1mhz, low jitter) ? on chip pll for fast pwm (32mhz, 48mhz, 64mhz) and cpu (12mhz, 16mhz); pll source rc & xtal ? dynamic clock switch ? temperature sensor ? operating voltage: 2.7v - 5.5v ? operating temperature: ? -40c to +105c or -40c to +125c ? operating speed ? 5v: 16mhz core, 64mhz pll ? 3.3v: 12mhz core, 48mhz pll 1. products configuration the different product configurations are described per table 1-1. notes: 1. flash size is 8kbytes for at90pwm81 and 16kbytes for at90pwm161. 2. ram size is 256 bytes for at90pwm81 and 1024 bytes for at90pwm161. table 1-1. pwm81/pwm161 configurations. package so20 qfn32 pins 20 32 flash size 8/16k (1) 8/16k (1) eeprom size 512 512 ram size 256/1024 (2) 256/1024 (2) psc 12 bits with extended features 1 1 psc 12 bits 1 1 timer 8 bits - - timer 16 bits 1 1 adc inputs 8 11 amplifiers for adc 1 1 temperature sensor 1 1 analog comparators 3 3 dac 1 1 dac amplifiers - - uart/dali - - spi 1 1 3 7734q?avr?02/12 at90pwm81/161 2. pin configurations figure 2-1. 20-pin packages. at90pwm 8 1/161 s o20 1 2 3 4 5 6 7 8 9 10 20 19 1 8 17 16 15 14 13 12 11 (acmp3_out/t1/pscout23) pb0 (reset/ocd/i n t2) pe0 (pscout20) pb1 (i n t0/pscout21) pb2 v cc g n d (acmp1_out/psci n 2/xtal1) pe1 (psci n r/acmp1m/xtal2) pe2 (pscoutr0/psci n rb) pd1 (adc0/acmp1) pd2 pb7 (adc9/icp1/pscout22) pb6 (adc 8 /acmp3/miso) pd6 (amp0+) pd5 (amp0-/adc7) pe3/aref/adc6 ag n d a v cc pb5 (adc5/i n t1/acmp2/sck) pb4 (adc3/acmpm/mosi) pb3 (pscoutr1/adc2/acmp2m) 4 7734q?avr?02/12 at90pwm81/161 figure 2-2. 32-pin packages. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nc (acmp3_out_a/ss/clko) pd0 (pscout20) pb1 (int0/pscout21) pb2 vcc gnd (acpm1_out/pscin2/xtal1) pe1 nc nc pd5 (amp0-/adc7) pe3/aref/adc6 agnd avcc pb5 (adc5/int1/sck/acmp2) pd4 (pscin2a/acmp3m/adc4) nc 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc pe0 (reset/ocd/int2) pb0 (pscout23/t1/acmp3_out) pb7 (adc9/pscout22/icp1) pd7 (adc10/pscinra) pb6 (adc8/miso/acmp3) pd6 ( amp0+ ) nc at90pwm81/161 qfn 32 5*5 nc (pscinr/acmp1m/xtal2) pe2 (pscoutr0/pscinrb) pd1 (adc0/acmp1) pd2 (adc1/acmp2_out) pd3 (adc2/acmp2m/pscoutr1) pb3 (adc3/acmpm/mosi) pb4 nc 5 7734q?avr?02/12 at90pwm81/161 table 2-1. functions description. mnemonic name, function & alternate function gnd ground: 0v reference agnd analog ground: 0v reference for analog part v cc power supply av cc analog power supply: this is the power supply voltage for analog part for a normal use this pin must be connected. aref analog reference: reference for analog converter. this is the reference voltage of the a/d converter. as output, can be used by external analog clko system clock output reset# ocd reset input on chip debug i/o xtal1 xtal input xtal2 xtal output miso spi master in slave out mosi spi master out slave in sck spi clock ss spi slave select intn external interrupt n tn timer n clock input pscoutxn pscx output n pscinx pscx digital input pscout0n psc reduced output n pscinr psc reduced digital input acmpn analog comparator n positive input acmpmn analog comparator n negative input acmpm negative input for analog comparators acompn_out analog comparator n output ampn- analog differential amplifier n input channel ampn+ analog differential amplifier n input channel adcn analog converter input channel n 6 7734q?avr?02/12 at90pwm81/161 table 2-2. pin out description. 2.1 pin descriptions 2.1.1 v cc digital supply voltage. 2.1.2 gnd ground. 2.1.3 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various sp ecial features of the at90pwm81/161 as listed on table 9-3 on page 75 . port so 20 pins qfn32 pins gp psc adc analog pb0 1 30 t1 pscout23 acmp3_out pe0 2 31 reset# ocd, int2 pd0 na 2 clko, ss acmp3_out_a pb1 3 3 pscout20 pb2 4 4 int0 pscout21 vcc 5 5 power supply gnd 6 6 ground pe1 7 7 xtal1 pscin2 acmp1_out pe2 8 10 xtal2 pscinr acmp1m pd1 9 11 pscoutr0, pscinrb pd2 10 12 adc0 acmp1 pd3na 13 adc1acmp2_out pb3 11 14 pscoutr1 adc2 acmp2m pb4 12 15 mosi adc3 acmpm pd4 na 18 pscin2a adc4 acmp3m pb5 13 19 int1, sck adc5 acmp2 avcc 14 20 analog supply agnd 15 21 analog ground 16 22 aref, analog ref adc6 pd5 17 23 adc7 amp0- pd6 18 26 amp0+ pb6 19 27 miso adc8 acmp3 pd7 na 28 pscinra adc10 pb7 20 29 icp1 pscout22 adc9 7 7734q?avr?02/12 at90pwm81/161 2.1.4 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the at90pwm81/161 as listed on table 9-6 on page 78 . 2.1.5 port e (p32..0) reset /xtal1/xtal2/aref port e is an 4-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the rstdisbl fuse is programmed, pe0 is used as an i/o pin. note that the electrical char- acteristics of pe0 differ from those of the other pins. if the rstdisbl fuse is unprogrammed, pe0 is us ed as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 7-1 on page 51 . shorter pulses are not guaranteed to generate a reset. depending on the clock selection fuse settings, pe1 can be used as input to the inverting oscil- lator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pe2 can be used as output from the inverting oscillator amplifier. the various special features of port e are elaborated in table 9-9 on page 80 and section ?clock systems and their distribution?, page 27 . 2.1.6 av cc av cc is the supply voltage pin for the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the ad c is used, it should be connected to v cc through a low- pass filter. 8 7734q?avr?02/12 at90pwm81/161 3. avr cpu core 3.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 architectural overview figure 3-1. block diagram of the avr architecture. in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 9 7734q?avr?02/12 at90pwm81/161 the fast-access register file contains 32 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-register , y-register, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16-bit or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm (store program memory) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher is the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the at90pwm81/161 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 3.3 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set summary? on page 301 for a detailed description. 10 7734q?avr?02/12 at90pwm81/161 3.4 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the ?instruction set summary? on page 301 . this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set to enabled the interrupts. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the ?instruction set summary? on page 301 . ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set summary? on page 301 for detailed information. ? bit 4 ? s: sign bit, s = n ? v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set summary? on page 301 for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetic. see the ?instruction set summary? on page 301 for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set summary? on page 301 for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set summary? on page 301 for detailed information. bit 76543210 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 11 7734q?avr?02/12 at90pwm81/161 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set summary? on page 301 for detailed information. 3.5 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 3-2 shows the structure of the 32 general purpose working registers in the cpu. figure 3-2. avr cpu general purpose working registers. most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 3-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 3.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 3-3 on page 12 . 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 12 7734q?avr?02/12 at90pwm81/161 figure 3-3. the x-register, y-register, and z-register. in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see ?instruction set summary? on page 301 for details). 3.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x100. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 3.7 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 1514131211109 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 00000000 13 7734q?avr?02/12 at90pwm81/161 figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 3-4. the parallel instruction fetches and instruction executions. figure 3-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 3-5. single cycle alu operation. 3.8 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in orde r to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see the section ?memory program- ming? on page 248 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 62 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is psc2 capt ? the psc2 capture event. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcu cr). refer to ?interrupts? on page 62 for more infor- mation. the reset vector can also be moved to the start of the boot flash section by clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 14 7734q?avr?02/12 at90pwm81/161 programming the bootrst fuse, see ?boot loader support ? read-while-write self-pro- gramming? on page 233 . 3.8.1 interrupt behavior when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling rout ine, and hardware clears the corresponding inter- rupt flag. interrupt flags can also be cleared by wr iting a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and re membered until the inte rrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt condit ions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) w ill be set and remembered until the global interrupt enable bit is set, and will th en be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction before any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 16 7734q?avr?02/12 at90pwm81/161 4. memories this section describes the different memories in the atmel at90pwm81/161. the avr architec- ture has two main memory spaces, the data memory and the program memory space. in addition, the at90pwm81/161 features an eeprom memory for data storage. all three mem- ory spaces are linear and regular. 4.1 in-system reprogrammable flash program memory the at90pwm81/161 contains 8/16kbytes on-chip in-system reprogrammable flash memory for program storage. since all avr instructions ar e 16 or 32 bits wide, the flash is organized as 4k 16bits for the at90pwm81, and 8k 16bits for the at90pwm161. for software security, the flash program memory space is divided into two sections, boot program section and appli- cation program section. the flash memory has an endurance of at leas t 10,000 write/erase cycles. the at90pwm81 program counter (pc) is 12 bits wide, thus addressing the 8kbytes program memory locations. the at90pwm161 program counter (pc) is 13 bits wide, thus addressing the 16kbytes pro- gram memory locations. the operation of boot program section and associated boot lock bits for software protection are described in detail in ?boot loader support ? read-while-write self- programming? on page 233 . ?memory programming? on page 248 contains a detailed descrip- tion on flash programming in spi or parallel programming mode. constant tables can be allocated within the entire program memory address space (see the description of lpm ? load program memory in ?instruction set summary? on page 301 ). timing diagrams for instruction fetch and execution are presented in ?instruction execution tim- ing? on page 12 . figure 4-1. program memory map. 0x0000 0x0fff/0x1fff program memory application flash section boot flash section 17 7734q?avr?02/12 at90pwm81/161 4.2 sram data memory figure 4-2 shows how the atmel at90pwm81/161 sram memory is organized. the at90pwm81/161 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instruc- tions can be used. the lower 512 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sram. the firs t 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 256 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y-register or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i /o registers, 160 extended i/o registers, and the 256/1024 bytes of internal data sram in the at90pwm81/161 are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 11 . figure 4-2. data memory map. 4.2.1 sram data access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 4-3 on page 18 . 32 registers 64 i/o registers internal sram (256/1024 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 0x01ff/0x04ff 18 7734q?avr?02/12 at90pwm81/161 figure 4-3. on-chip data sram access cycles. 4.3 eeprom data memory the at90pwm81/16 1 contains 512 bytes of data eeprom memory. it is orga nized as a sepa- rate data space, in which sing le bytes can be read and writ ten. the eeprom has an endurance of at least 100,000 write/ erase cycles. the access betwee n the eeprom and the cpu is described in the following, specifying the e eprom address registers, the eeprom data reg- ister, and the eeprom control register. for a detailed description of spi and parallel data downloading to the eeprom, see ?serial downloading? on page 261 , and ?parallel programming parameters, pin mapping, and com- mands? on page 252 respectively. 4.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 4-2 on page 21 . a self-timing function, however, lets the user software detect when the nex t byte can be written. if the user code con- tains instructions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. for details on how to avoid problems in these situations see ?preventing eeprom cor- ruption? on page 25 . in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cp u is halted for two clock cycles before the next instruction is executed. clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 19 7734q?avr?02/12 at90pwm81/161 4.3.2 eearh and eearl - eeprom address registers ? bits 15..9 ? reserved bits these bits are reserved bits in the at 90pwm81/161 and will always read as zero. ? bits 8..0 ? eear8..0: eeprom address the eeprom address registers ? eearh and eearl specify the eeprom address in the 512 bytes eeprom space. the eeprom data bytes are ad dressed linearly between 0 and 511. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 4.3.3 eedr - eeprom data register ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 4.3.4 eecr - eeprom control register ? bits 7 ? nvmbsy: non-volatile memory busy the nvmbsy bit is a status bit that indicates that the nvm memory (flash, eeprom, lock- bits) is busy programming. once a program operation is started, the bit will be set and it remains set until the program operation is completed. bits 6 ? eepage: eeprom page ac cess (multiple by tes access mode) writing eepage to one enables the multiple bytes access mode. that means that several bytes can be programmed simultaneously into the eeprom. when the eepage bit has been written to one, the eepage bit remains set until an eeprom program operation is completed. alterna- tively the bit is cleared when the temporary eeprom buffer is flushed in software (see eepmn bits description). any write to eepage while eepe is one will be ignored. see section ?program multiple bytes in one atomic operation?, page 21 for details on how to load data into the temporary eeprom pa ge and the usage of the eepage bit. bit 1514131211 10 9 8 ????? ? ?eear8eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543 2 10 read/write r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 x xxxxx x xx bit 76543210 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 765432 10 nvmbsy eepage eepm1 eepm0 eerie eemwe eewe eere eecr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x 0 0 x 0 20 7734q?avr?02/12 at90pwm81/161 ? bits 5..4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting define s which programming acti on that will be trig- gered when writing eewe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 4-1 . while eewe is set, any write to eep mn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant inter- rupt when eewe is cleared. th e interrupt will not be generated during ee prom write or spm. ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to one causes the eeprom to be written. when eemwe is set, setting eewe within four cl ock cycles will write data to the eeprom at the selected address if eemwe is zero, sett ing eewe will have no e ffect. when eemwe has been written to one by software, hardware clears th e bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be written to one be fore a logical one is written to eewe, oth- erwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program mem- ory control and status register) becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writing a zero to eewe in eecr. 6. within four clock cycles after sett ing eemwe, write a logical one to eewe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is co mpleted before initiating a new eeprom write. step 2 is only relevant if the software contai ns a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming? on page 233 for details about boot programming. table 4-1. eeprom mode bits. eepm1 eepm0 programming time operation 0 0 3.4ms erase and write in one operation (atomic operation) 0 1 1.8ms erase only 1 0 1.8ms write only 1 1 ? flush temporary eeprom page buffer 21 7734q?avr?02/12 at90pwm81/161 caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom acce ss, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bit is cleared by hardware. the user soft- ware can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the re ad strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. the user should poll the eewe bit before starti ng the read operation. if a write operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 4-2 lists the typical pro- gramming time for eeprom access from the cpu. 4.3.5 program multiple bytes in one atomic operation it is possible to write multiple bytes into the eeprom. before initiating a programming (erase/write), the data to be written has to be loaded into the temporary eeprom page buffer. writing eepage to one enabl es a load operation. when eepage bit is written to o ne, the temporary eeprom page bu ffer is ready for loading. to load data into the temporary eeprom page buffer, the address and data must be written into eearl and eedr respectively. note that the data is loaded w hen eedr is updat ed. therefore, the address must be written before data. this operation is repeated until the temporary eeprom page buffer is filled up or until all data to be written have been loaded. the number of bytes that is loaded must not exceed the te mporary eeprom page size before performing a program operation. note that it is not possible to write more than one time to each byte in the temporary eeprom page buffer before execut ing a program operation. if the same byte is writ- ten multiple times, th e content in the tem porary eeprom page will be bi t wise and between the written data (that is, if 0xaa and 0x55 is loaded to the same byte, the result will be 0x00). the temporary eeprom buffer will be ready for new data after the progra m operation has com- pleted. alternatively, the temp orary eeprom buffer is flushed a nd ready for new data by writing eepe (within four cycles after eem pe is written) if the eepmn bi ts are 0b11. when the tempo- rary eeprom buffer is flushed, the eepage bit wi ll be cleared. loading da ta into the temporary eeprom buffer takes three cpu clock cycles. if eedr is written while eepage is set, the cpu is halted to ensure that th e operation takes three cycles. table 4-2. eeprom programming time. symbol number of calibrat ed rc oscillator cycles typical programming time eeprom write (from cpu) 26368 3.3ms 22 7734q?avr?02/12 at90pwm81/161 the order the different bits and registers should be accessed is: 1 write eepage in eecr (loading of temp orary eeprom buff er is enabled). 2 write the address bits needed to address bytes within a page into eearl. 3 write data to eedr. 4 repeat 2 and 3 above until t he buffer is filled up or until all data is loaded. 5 write the remaining addre ss bits into eearh:eearl. a. select which progra mming mode that shou ld be executed (eepmn bits). write the eepe bit in eecr (within four cycles after eempe has been written) to start a program opera- tion. the temporary eeprom page buffer will auto-erase after program operation is completed. or b. if an error situation occurred and the loading should be terminated by software: write eepm1:0 to 0b11 and trigger the flushing by writing eepe (within four cycles after eempe has been written). 4.4 fuse bits the at90pwm81/161 has three fuse bytes. table 4-3 through table 4-5 on page 23 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. see table 7-2 on page 53 for bodlevel fuse decoding. table 4-3. extended low fuse byte. extended fuse byte bit no. description de fault value psc2rb 7 psc2 reset behavior 1 psc2rba 6 psc2 reset behavior for out22 & 23 1 pscrrb 5 psc reduced reset behavior 1 pscrv 4 pscout & pscoutr reset value 1 pscinrb 3 psc & pscr inputs reset behavior 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 0 (programmed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) 23 7734q?avr?02/12 at90pwm81/161 notes: 1. see ?alternate functions of port e? on page 80 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?watchdog timer configuration.? on page 60 for details. 4. the default value of bootsz1..0 results in maximum boot size. note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 5-4 on page 30 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8mhz. see table 5-1 on page 28 for details. 3. the ckout fuse allows the system clock to be output on portd0. see ?clock output buffer? on page 34 for details. 4. see ?system clock prescaler? on page 39 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. table 4-4. fuse high byte. high fuse byte bit no. de scription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer alwa ys on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bootsz1 2 select boot size (see table 20-7 on page 246 for details) 0 (programmed) (4) bootsz0 1 select boot size (see table 20-7 on page 246 for details) 0 (programmed) (4) bootrst 0 select reset vector 1 (unprogrammed) table 4-5. fuse low byte. low fuse byte bit no. de scription default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock so urce 0 (programmed) (2) cksel2 2 select clock so urce 0 (programmed) (2) cksel1 1 select clock so urce 1 (unprogrammed) (2) cksel0 0 select clock so urce 0 (programmed) (2) 24 7734q?avr?02/12 at90pwm81/161 4.4.1 code examples the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts ar e controlled (for example, by disabling inter- rupts globally) so that no inte rrupts will occur during execution of these functi ons. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait fo r any ongoing spm co mmand to finish. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 27 7734q?avr?02/12 at90pwm81/161 5. system clock and clock options the atmel at90pwm81/161 provides a large number of clock sources. those can be divided in two categories: internal and external. after reset, cksel fuses select one clock source. once the device is running, software clock switching is available on any other clock sources. some hardware controls are provided for clo ck switching management but some specific proce- dures must be observed. some settings may lead the user to program the device in an inadequate configuration. 5.1 clock systems and their distribution figure 5-1 presents the principal clock systems in the avr and their distribution. all of the clocks may not be active at a given time. in order to reduce power consumption, the clocks from mod- ules not being used can be halted by using different sleep modes or by using features of the dynamic clock switch ( ?power management and sleep modes? on page 45 or ?dynamic clock switch? on page 35 ). the clock systems are detailed below. figure 5-1. clock distribution. 5.1.1 clk cpu - cpu clock the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general pur pose register file, the status register and the general i/o modules adc cpu core ram clk i/o avr clock control unit clk cpu flash and eeprom clk flash clk adc source clock watchdog timer watchdog oscillator reset logic watchdog clock calibrated rc oscillator (crystal oscillator) external clock psc2/pscr pll clk pll multiplexer pll input prescaler clock switch xtal2 xtal1 ckout fuse clko clk pll /4 28 7734q?avr?02/12 at90pwm81/161 data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 5.1.2 clk i/o - i/o clock the i/o clock is used by the majority of the i/o modules, like timer/counter. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. 5.1.3 clk flash - flash clock the flash clock controls operation of the flash in terface. the flash clock is usually active simul- taneously with the cpu clock. 5.1.4 clk pll - pll clock the pll clock allows the psc modules to be cloc ked directly from a 64/32mhz clock. a 16mhz clock is also derived for the cpu. 5.1.5 clk adc - adc clock the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 5.2 clock sources the device has the following clock source options, selectable by flash fuse bits (default) or by the clkselr register (dynamic clock switch circuit) as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. table 5-1. device clocking options select (1) , pll source and pe1 and pe2 functionality. device clocking option system clock pll input (2) cksel3..0 (3) csel3..0 (4) pe1 pe2 external clock ext clk (8) rc osc (6) 0000 clki i/o pll output divided by 4 : 16mhz driven by internal rc pll / 4 rc osc (6) 0001 i/o i/o calibrated internal rc oscillator 8mhz rc osc (6) rc osc (6) 0010 i/o i/o internal 128khz rc oscillator (wd) wd (7) n/a 0011 i/o i/o pll output divided by 4 / pll driven by external crystal/ceramic resonator pll / 4 ext osc (5) 0100 xtal1 xtal2 pll output divided by 4/ pll driven by external clock pll / 4 ext clk (8) 0101 clki i/o calibrated internal rc oscillator 1mhz rc osc (6) n/a 0110 i/o i/o external crystal/ceramic resona tor (3.0mhz - 8.0mhz) ext osc (5) ext osc (5) 0111 b xtal1 xtal2 external crystal/ceramic resona tor (0.9mhz - 3.0mhz) ext osc (5) rc osc (6) 1000 b xtal1 xtal2 external crystal/ceramic resona tor (0.9mhz - 3.0mhz) ext osc (5) rc osc (6) 1001 b xtal1 xtal2 external crystal/ceramic resona tor (3.0mhz - 8.0mhz) ext osc (5) rc osc (6) 1010 b xtal1 xtal2 external crystal/ceramic resona tor (3.0mhz - 8.0mhz) ext osc (5) rc osc (6) 1011 b xtal1 xtal2 external crystal/ceramic resona tor (3.0mhz - 8.0mhz) ext osc (5) rc osc (6) 1100 b xtal1 xtal2 29 7734q?avr?02/12 at90pwm81/161 note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 2. pll must be driven by a nominal 8mhz clock source. 3. flash fuse bits. 4. clkselr register bits. 5. ext osc: external oscillator. 6. rc osc: internal rc oscillator (1mhz or 8mhz). 7. wd: internal watch dog rc oscillator 128khz. 8. ext clk: external clock input. the various choices for each clocking opti on is given in the following sections. when the cpu wakes up from power-down, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring sta- ble oscillator operation before instruction exec ution starts. when the cpu starts from reset, there is an additional delay allowing the power to reach a sta- ble level before commencing normal operation. the watchdog oscillator is used for timing this real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 5-2 . 5.2.1 default clock source the device will always starts up from reset using the clock s ource defined by cksel fuses the start-up time defined by sut fuses . this configuration is latche d in clkselr register at reset. the device will always starts up at power-on using the clock source defined by clkselr regis- ter (csel3..0 and csut1:0). the device is shipped with cksel fuses = 0010 b , sut fuses = 10 b , and ckdiv8 fuse pro- grammed. the default clock sour ce setting is therefore the in ternal rc oscillator running at 8mhz with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired cl ock source setting using an in-system or high- voltage programmer. this set-up must be taken into account when using isp tools. 5.2.2 calibrated internal rc oscillator by default, the internal rc oscillator provides an approximate 8.0mhz clock or a 1mhz clock. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. external crystal/ceramic resona tor (3.0mhz - 8.0mhz) ext osc (5) rc osc (6) 1101 b xtal1 xtal2 external crystal/ceramic resona tor (8.0mhz - 16.0mhz) ext osc (5) rc osc (6) 1110 b xtal1 xtal2 external crystal/ceramic resona tor (8.0mhz - 16.0mhz) ext osc (5) rc osc (6) 1111 b xtal1 xtal2 table 5-1. device clocking options select (1) , pll source and pe1 and pe2 functionality. (continued) device clocking option system clock pll input (2) cksel3..0 (3) csel3..0 (4) pe1 pe2 table 5-2. number of watchdog oscillator cycles. typical time-out number of cycles 4ms 512 64ms 8k (8,192) 30 7734q?avr?02/12 at90pwm81/161 the switch between 8mhz and 1mhz is done by the ckrc81 bit in mcucr register. see ?mcucr - mcu control register? on page 42 for more details.the rc oscillator can be accessed by two cksel or csel configurations. at reset, the ckrc81 bi t is initialised with the value compatible with cksel value (1 for cksel3 ..0 = 0110, 0 for all other values). the rc oscillator is active for any cksel3..0 or csel3..0 configuration w here it is used as sys- tem clock or pll source clock. the rc osc illator is diabled in th e following cksel3..0 or csel3..0 cases: ? 0011 (128k oscillator) ? 0100, 0101 (pll/4 system clock driven by external clock or oscillator) ? 1100, 1101 (external oscillator) the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 39 for more details. this clock may be select ed as the system clock by programming the cksel fuses or csel field as shown in table 5-1 on page 28 . if selected, it will operate with no external components. during reset, hardware loads the calibration byte into the osccal regis- ter and thereby automatically calibrates the rc oscillator. the accuracy of this calibration is shown as factory calibration in table 22-1 on page 270 . by changing the osccal register from sw, see ?osccal ? oscillator ca libration register? on page 39 , it is possible to get a higher calibration accuracy than by using the factory calibration. the accuracy of this calibration is shown as user calibration in table 22-1 on page 270 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed cali- bration value, see the section ?calibration byte? on page 252 . notes: 1. the device is shipped with this option selected. 2. the frequency ranges are preliminary values. actual values are tbd. 3. if 8mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. 4. switch between 8mhz and 1mhz is done by ckrc81 bit in mcucr register. when this oscillator is selected, start-up time s are determined by the sut fuses as shown in table 5-4 on page 30 . note: 1. if the rstdisbl fuse is programmed , this start-up time will be increased to 14ck + 4.1ms to ensure programming mode can be entered. 2. the device is shipped with this option selected. table 5-3. internal calibrated rc o scillator operating modes (1)(3) . frequency range (2) (mhz) cksel3..0 7.6 - 8.4 0010 0.95 - 1.05 (4) 0010 table 5-4. start-up times for the internal calib rated rc oscillator clock selection. power conditions start-up time from power- down additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck (1) 00 fast rising power 6ck 14ck + 4.1ms 01 slowly rising power 6ck 14ck + 65ms (2) 10 reserved 11 31 7734q?avr?02/12 at90pwm81/161 5.2.2.1 rc oscillator calibration at factory the rc oscillator is calibrated at 3v, 25c for an 8mhz target frequency with an accuracy 1%. the corresponding value oscal (@amb.) is st ored in the signature row and automatically loaded in the oscal register at reset. the rc oscillator is monitored at 105c or 125 c (versus product version) with an accuracy within 5% limits. 5.2.3 128khz internal oscillator the 128khz internal oscillator is a low power oscillator providing a clock of 128khz. the fre- quency is nominal at 3v and 25c. this cl ock may be select as the system clock by programming cksel fuses or csel field as shown in table 5-1 on page 28 . when this clock source is selected, start-up times are determined by the sut fuses or by csut field as shown in table 5-5 . notes: 1. flash fuse bits. 2. clkselr register bits. 5.2.4 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 5-2 on page 31 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 5-6 . for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 5-2. crystal oscillator connections. table 5-5. start-up times for the 128k hz internal oscillator. sut1..0 (1) csut1..0 (2) start-up time from power- down additional delay from reset recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4ms fast rising power 10 6 ck 14ck + 64ms slowly rising power 11 reserved xtal2 xtal1 gnd c2 c1 32 7734q?avr?02/12 at90pwm81/161 the oscillator can operate in three different mo des, each optimized for a specific frequency range. the operating mode is selected by cksel3..1 fuses or by csel3..1 field as shown in table 5-6 . notes: 1. flash fuse bits. 2. clkselr register bits. 3. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses or csel0 together with csut1..0 field select the start-up times as shown in table 5-7 . notes: 1. flash fuse bits. 2. clkselr register bits. 3. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 4. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. table 5-6. crystal oscillator operating modes. cksel3..1 (1) csel3..1 (2) frequency range [mhz] recommended range for capacitors c1 and c2 for use with crystals [pf] 100 (3) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 table 5-7. start-up times for the crysta l oscillator clock selection. cksel0 (1) csel0 (2) sut1..0 (1) csut1..0 (2) start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258ck (3) 14ck + 4.1ms ceramic resonator, fast rising power 0 01 258ck (3) 14ck + 65ms ceramic resonator, slowly rising power 0 10 1k (1024)ck (4) 14ck ceramic resonator, bod enabled 0 11 1k (1024)ck (4) 14ck + 4.1ms ceramic resonator, fast rising power 1 00 1k (1024)ck (4) 14ck + 65ms ceramic resonator, slowly rising power 1 01 16k (16384)ck 14ck crystal oscillator, bod enabled 1 10 16k (16384)ck 14ck + 4.1ms crystal oscillator, fast rising power 1 11 16k (16384)ck 14ck + 65ms crystal oscillator, slowly rising power 33 7734q?avr?02/12 at90pwm81/161 5.2.5 external clock to drive the device from this external clock source, clki should be driven as shown in figure 5- 3 . to run the device on an exter nal clock, the cksel fuses or csel field must be programmed as shown in table 5-1 on page 28 . figure 5-3. external clock drive configuration. when this clock source is selected, start-up times are determined by the sut fuses or csut field as shown in table 5-8 . notes: 1. flash fuse bits. 2. clkselr register bits. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 39 for details. 5.2.6 pll to generate high frequency and accurate pwm waveforms, the ?psc?s need high frequency clock input. this clock is generated by a pll. to keep all pwm accuracy, the frequency factor of pll must be configured by software. the internal pll in at90pwm81/161 generates a clock frequency multiplied from nominally 8mhz input. the source of the 8mhz pll input clock can be selected from three possible sources (see the figure 5-4 on page 34 ): ? internal rc oscillator ? crystal oscillator ? external clock the internal pll is enabled only when the plle bit in the register pllcsr is set. the bit plock from the register pllcsr is set when pll is locked. when selected as clock source by fuse, the pll mu ltiplication factor is initialized at the value of 6, compatible with a 3v supply. table 5-8. start-up times for the external clock selection. sut1..0 (1) csut1..0 (2) start-up time from power-down additional delay from reset recommended usage 00 6ck 14ck bod enabled 01 6ck 14ck + 4ms fast rising power 10 6ck 14ck + 64ms slowly rising power 11 reserved clki (xtal1) gnd external clock signal 34 7734q?avr?02/12 at90pwm81/161 the pll is locked on the source oscillator whic h must remains close to 8mhz to assure proper lock of the pll. both internal rc oscillator and pll are switched off in power-down and standby sleep modes figure 5-4. pck clocking system. 5.2.7 clock output buffer the device can output the system clock on t he clko pin. to enable the output, the ckout fuse or cout bit of clkselr regi ster has to be programmed. this mode is suitable when the chip clock is used to drive other circuits on th e system. note that the clock will not be output dur- ing reset and the normal operati on of i/o pin will be overridden when the fuses are programmed. any clock source can be selected when the clock is output on clko. if the system clock pres- caler is used, it is the divided system clock that is output. table 5-9. start-up times when the pll is selected as system clock. cksel3..0 sut1..0 start-up time from power- down additional delay from reset (v cc = 5.0v) clock source 0100 00 1k ck 14ck external crystal or resonator 01 1k ck 14ck + 4ms 10 1k ck 14ck + 64ms 11 16k ck 14ck 0101 00 16k ck 14ck external clock 01 16k ck 14ck + 4ms 10 16k ck 14ck + 4ms 11 16k ck 14ck + 64ms 0001 00 1k ck 14ck internal rc oscillator 01 1k ck 14ck + 4ms 10 1k ck 14ck + 64ms rc oscillator osccal xtal1 xtal2 oscillators ck plle lock det ect or plock source divide by 4 clk pll cksel3..0 8mhz pll *n pllf3..0 35 7734q?avr?02/12 at90pwm81/161 5.3 dynamic clock switch 5.3.1 features at90pwm81/161 provides a powerful dynamic clock switch that allows users to turn on and off clocks of the device on the fly. the built-in de-glitching circuitry allows clocks to be enabled or disabled asynchronously. this enables effici ent power management schemes to be imple- mented easily and quickly. in a safety applic ation, the dynamic clock switch circuit may continuously monitor the external clock fails. the at90pwm81/161 provides one register for clock fuse substitution (clkselr) and one register to control the dynamic clock switch ci rcuit (clkcsr). the watchdog is used to monitor external clock source if needed. the control of the dynamic clock switch circuit must be super- vised by software. the low level control is performed by hardware through the clkcsr register. the features are: ? safe commands , to avoid unintentional commands, a special write procedure must be followed to change the clkcsr register bits ( see ?clkcsr ? clock control & status register? on page 42 ): ? exclusive action , the actions are controlled by a decoding (command table). the main commands of the dynamic clock switching are: ?? disable clock source ?, ?? enable clock source ?, ?? request for clock availability ?, ?? clock source switching ?, ?? recover system clock source ?. ? status , a status on the availability of the enabled clock and the code recovering of clock source used to drive the system clock are provided. 5.3.2 fuses substitution during reset, bits of the low fuse byte are latched in the clkselr register. the content of this register can operate as well as the low fuse byte. cksel 3..0, sut1.. 0 and ckout fuses are substituted as shown in figure 5-5 and replaced respectively by csel3..0, csut1:0 and cout. 5.3.3 clock source selection the available codes of clock source is given are in table 5-1 on page 28 . 36 7734q?avr?02/12 at90pwm81/161 figure 5-5. fuses substitution and cl ock source selection. when ? enable/disable clock source ?, ? request for clock availability ? or ? clock source switching ? command is entered, the selected configuratio n provided by the clkselr register is latched for each targeted clock source. ? recover system clock source ? command enables the code recovering of clock source used to drive the system clock. the cksel field of clkselr register is then updated with this code. there is no information on the sut used or status on ckout. because the selected configuration is latched at cl ock source level, it is possible to enable many clock sources at a given time (e x: the internal rc oscillator fo r system clock + an oscillator with external crystal). the user?s software has the responsibility of this management. ? request for clock availability? command returns the workin g order of the clock source addressed. the status is set in the clkrdy bit of clkcsr register. 5.3.4 enable/disable clock source ? enable clock source ? command selects and enables the clock source provided by the setting of clkselr register (csel3..0 and csut1:0). csel field will select the clock source and csut field will select the start-up time (as cksel and su t fuse bits do it). to be sure that a clock source has been enabled, it will be better to perform a ? request for clock availability? command after the ? enable clock source ? command. ? disable clock source ? command disables the clock source provided by the setting of clkselr register (only csel3..0). if the clock source is the one that is used to drive the system clock, the command is not taken into account. 5.3.5 clock availability ?request for clock availability? command enables an oscillation- counting of the selected source clock, csel3..0. the count is provided by cs ut1..0. the clock is declared ready (clkrdy = 1) when the count is finished. this flag remains unchanged up to a new count. the clkrdy flag is reset when the count starts. to perform this checking, the cksel and csut fields should not change all long the operation is running. two usages are possible: clksel[3..0] sut[1..0] ckout register: clkselr fuse: fuse low byte csel[3..0] csut[1..0] cout default r/w reg. sel decodeur sel-1 sel-0 sel-2 sel-n cksel[3..0] sut[1..0] sel encodeur en-1 en-0 en-2 en -n ckout reset sclkrq ( * ) sclkrq ( * ) : command of clock control & status register internal data bus selected configuration clock switch current configuration 37 7734q?avr?02/12 at90pwm81/161 1. clock stability before switching once the new clock source is selected, the count procedure is running. the user (code) should wait for the setting of the clkrdy fl ag in clkscr register before to perform a switching. 2. clock available on request at any time, the user (code) can ask for the av ailability of a clock so urce. the user (code) can request it writing the appropriate command in the clkscr register. a full status on clock sources then can be done. 5.3.6 clock switching to drive the system clock, the user can switch from the current clock source to the following ones (one of them is the current clock source): 1. calibrated internal rc oscillator 8.0mhz/1.0mhz, 2. internal watchdog oscillator 128khz, 3. external clock, 4. external crystal/ceramic resonator, 5. pll output divided by four. the clock switching is performed in a sequence of commands. first, the user (code) must make sure that the new clock source is running. then the switching command can be entered. at the end, the user (code) can stop the previous cloc k source. it will be bette r to run this sequence once the interrupts disabled. the user (code) has the responsibility of the clock switching sequence. 38 7734q?avr?02/12 at90pwm81/161 here is a ?light? c-code that describes such a sequence of commands. warning: in the at90pwm81/161, only one among the external clock sources can be enabled at a given time and it is not possible to switch from exter nal clock to external oscillator as both sources share one pin. also, it is not possible to switch the synchroni zation source of the pll when the sytem clock is pll/4. see table 5-1 on page 28 to identify these cases. as they are two csel adresses to access the calibrated internal rc o scillator 8.0mhz/1.0mhz, the change between the two frequencies is not allowed by the clock switching features. the ckrc81 bit in mcucr register must be used for this purpose. c code example void clockswiching (unsigned char clk-number, unsigned char sut) { #define clock-recover 0x05 #define clock-enable 0x02 #define clock-switch 0x04 #define clock-disable 0x01 unsigned char previous-clk, temp; // disable interrupts asm ("cli"); temp = sreg; // ?recover system clock source? command clkcsr = 1 << clkcce; clkcsr = clock-recover; previous-clk = clkselr & 0x0f; // ?enable clock source? command clkselr = ((sut << 4 ) & 0x30) | (clk-number & 0x0f); clkcsr = 1 << clkcce; clkcsr = clock-enable; // wait for clock availability while ((clkcsr & (1 << clkrdy)) == 0); // ?clock source switching? command clkcsr = 1 << clkcce; clkcsr = clock-switch; // wait for effective switching while (1){ clkcsr = 1 << clkcce; clkcsr = clock-recover; if ((clkselr & 0x0f) == (clk-number & 0x0f)) break; } // ?disable clock source? command clkselr = previous-clk; clkcsr = 1 << clkcce; clkcsr = clock-disable; // re-enable interrupts sreg = temp; asm ("sei"); } 39 7734q?avr?02/12 at90pwm81/161 5.4 system clock prescaler 5.4.1 features the at90pwm81/161 system clock can be divided by setting the clock prescaler register ? clkpr. this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used with al l clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 5-10 on page 40 . 5.4.2 switching time when switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu?s clock frequency. hence, it is not possible to determine the state of the prescaler ? even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 t2 before the new clock frequency is active. in this interv al, 2 active clock edges are produced. here, t1 is the previous clock period, and t2 is the perio d corresponding to the new prescaler setting. 5.5 register description 5.5.1 osccal ? oscillato r calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillator to remove process variations from the oscillator frequency . the factory-calibrate d value is automat- ically written to this register during chip reset, giving an oscilla tor frequency of 8.0mhz at 25c. the application software can write this register to cha nge the oscillator fre quency. the oscillator can be calibrated to any frequency in the range 7.6mhz - 8.4mhz within 1% accuracy. calibra- tion outside that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses , and these write times will be affected accordingly. if the eeprom or flash are writ ten, do not calibrate to more than 8.8mhz. otherwise, the eeprom or flash write may fail. the cal7..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. incrementing cal7 ..0 by 1 will give a frequency increm ent of less than 0.5% in the fre- quency range 7.6mhz - 8.4mhz. bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value 40 7734q?avr?02/12 at90pwm81/161 5.5.2 clkpr ? clock prescaler register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously wr itten to zero. clkpce is cleared by hardware four cycles af ter it is written or when the clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 6:4 ? res: reserved bits these bits are reserved bits in the at 90pwm81/161 and will always read as zero. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 5-10 . to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired va lue to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting in order not to disturb the procedure. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of eight at star t up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description table 5-10. clock prescaler select. clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 41 7734q?avr?02/12 at90pwm81/161 5.5.3 pllcsr - pll control and status register ? bit 7..3 ? res: reserved bits these bits are reserved bits in the at90pwm81/161 and always read as zero. ? bit 5..2-? pllf: pll factor the pllf bits is used to select the multiplication factor of the pll. note: pllf3 is used for debug purpose ( must be wired ). 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 5-10. clock prescaler select. (continued) clkps3 clkps2 clkps1 clkps0 clock division factor bit 76543210 $29 ($29) ? ? pllf3 pllf2 pllf1 pllf0 plle plock pllcsr read/write r r r/w r/w r/w r/w r/w r initial value 0 0 0 1 0 0 0/1 0 table 5-11. pll multiplication factor. pllf3..0 n+2 pll frequency [mhz] 7-f reserved 68 64 57 56 46 48 35 40 24 32 0-1 reserved 42 7734q?avr?02/12 at90pwm81/161 ? bit 1 ? plle: pll enable when the plle is set, the pll is started and if not yet started the in ternal rc oscillator is started as pll reference clock. if pll is selected as a system clock source the value for this bit is always 1. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock, and it is safe to enable clk pll for psc. the time to lock is specified in table 5-9 on page 34 . 5.5.4 mcucr - mcu control register notes: 1. value is initialized with the fuse cksel2. 2. value is initialized with fuses cksel3..0 (1 when cksel3..0= 0110, 0 in all other cases). ? bit 2? ckrc81: frequency selection of the calibrated 8/1mhz rc oscillator thanks to ckrc81 in mcucr sfr, the typi cal frequency of the calibrated rc oscillator is changed. ? when the ckrc81 bit is written to zero , the rc oscillator frequency is 8mhz. ? when the ckrc81 bit is written to one, the rc oscillator frequency is 1mhz. note: this bit only can be changed on ly when the rc oscillator is enabled. note: when the rc oscillato r is used as the pll source, ckrc81 must not be written to 1. note: if the rc oscillator is disabled, this bit is cleared by hardware. 5.5.5 clkcsr ? clock control & status register ? bit 7 ? clkcce: clock control change enable the clkcce bit must be written to logic one to enable change of the clkcsr bits. the clkcce bit is only updated when the other bits in clkcsr are simultaneo usly written to zero. clkcce is cleared by hardware four cycles af ter it is written or when the clkcsr bits are written. rewriting the clkcce bit within this time-out period does neither extend the time-out period, nor clear the clkcce bit. ? bits 6:5 ? res: reserved bits these bits are reserved bits in the at 90pwm81/161 and will always read as zero. ? bits 4 ? clkrdy: clock ready flag this flag is the output of the ? clock availability ? logic. this flag is reset once the ? request for clock availability ? command is entered. it is set when ? clock availability ? logic confirms that the (selected) clock is running and is stable. the delay from the request and the flag setting is no t fixed, it depends on the clock start-up time, bit 76543210 ? ? ? pud rstdis ckrc81 ivsel ivce mcucr read/writerrrr/wr/wr/wr/wr/w initial value00000/1 (1) 000 bit 7 6 5 4 3 2 1 0 clkcce ? ? clkrdy clkc3 clkc2 clkc1 clkc0 clkcsr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 43 7734q?avr?02/12 at90pwm81/161 the clock frequency and, of course, if the clock is alive. the user?s has itself to do the difference between ? no_clock_signal ? and ? clock_signal_not_yet_available ?. ? bits 3:0 ? clkc3:0: clock control bits 3 - 0 these bits define the command to provide to the ? clock switch? module. the special write procedure must be followed to change the clkc bits ( see ?bit 7 ? clkcce: clock control change enable? on page 42 ). 1. write the clock control change enable (clkcce) bit to one and all other bits in clkcsr to zero. 2. within four cycles, write the desired value to clkcsr register while clearing clkcce bit. interrupts should be disabled when setting clkcsr register in order not to disturb the procedure. 5.5.6 clkselr - clock selection register ? bit 7? res: reserved bit this bit is reserved bit in the at90 pwm81/161 and will always read as zero. ? bit 6 ? cout: clock out the cout bit is initialized with ckout fuse bit. the cout bit is only used in case of ? ckout ? command. refer to section 5.2.7 ?clock output buffer? on page 34 for using. in case of ? recover system clock source ? command, cout it is not affected (no recovering of this setting). ? bits 5:4 ? csut1:0: clock start-up time csut bits are initialized with the values of sut fuse bits. in case of ? enable/disable clock source ? command, csut field provides the code of the clock start-up time. refer to subdivisions of section 5.2 ?clock sources? on page 28 for code of clock table 5-12. clock command list. clock command clkc3..0 no command 0000 b disable clock source 0001 b enable clock source 0010 b request for clock availability 0011 b clock source switch 0100 b recover system clock source code 0101 b ckout command 0111 b no command 1xxx b bit 7 6 543210 - cout csut1 csut0 csel3 csel2 csel1 csel0 clkselr read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 ckout fuse sut1..0 fuses cksel3..0 fuses 44 7734q?avr?02/12 at90pwm81/161 start-up times. in case of ? recover system clock source ? command, csut field is not affected (no recovering of sut code). ? bits 3:0 ? csel3:0: clock source select csel bits are initialized with the values of cksel fuse bits. in case of ? enable/disable clock source ?, ? request for clock availability ? or ? clock source switch ? command, csel field gets back the code of the clock source. refer to table 5-1 on page 28 and subdivisions of section 5.2 ?clock sources? on page 28 for clock source codes. in case of ? recover system clock source ? command, csel field receives the code of the clock source used to drive the clock control unit as described in figure 5-1 on page 27 . 45 7734q?avr?02/12 at90pwm81/161 6. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. 6.1 sleep modes figure 5-1 on page 27 presents the different clock systems in the at90pwm81/161, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 6-1 shows the different sleep modes, their wake up sources. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. only level interrupt. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc nois e reduction, power-down or sta ndby) will be activated by the sleep instruct ion. see table 6-2 on page 48 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. 6.2 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing spi, anal og comparator, adc, timer/counters, watch- dog, and the interrupt system to continue operating. this sleep mode basically halt clk cpu and clk flash , while allowing the ot her clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by clearing the acnen bit in the analog comparator control and status register ? acncon. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. table 6-1. active clock domains an d wake-up sources in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk pll main clock source enabled int3..0 psc spm/eeprom ready adc wdt other/o idle x x x x x x x x x x adc noise reduction xx x x (2) xxxx power- down x (2) x standby (1) xx (2) x 46 7734q?avr?02/12 at90pwm81/161 6.3 adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, timer/counter (if their clock source is external - t0 or t1) and the watchdog to continue operat- ing (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the ad c, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a timer/counter in terrupt, an spm/eeprom read y interrupt, an exte rnal level interrupt on int2:0 can wake up the mcu from adc noise reduction mode. 6.4 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external oscillator is stopped, while the external interrupts and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, a psc interrupt, an external level interrupt on int2:0 can wake up the mcu. this sleep mode basically halts all generated clocks, allowi ng operation of asynchronous mod- ules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 83 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 28 . 6.5 standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. fr om standby mode, the device wakes up in six clock cycles. 6.6 power reduction register the power reduction register, prr, provides a method to stop the clock to individual peripher- als to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the perip heral should in most cases be disabled before stopping the clock. waking up a module, which is done by clear ing the bit in prr, puts the module in the same state as before shutdown. a full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping and starting of its clock. so its recommended to stop a peripheral before stopping its clock with prr register. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. in all other sleep modes, the clock is already stopped. 47 7734q?avr?02/12 at90pwm81/161 6.7 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 6.7.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an exten ded conversion. refer to ?adc noise canceler? on page 210 for details on adc operation. 6.7.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is not automatically disabled, so it should be dis- abled if not used. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage ref- erence will be enabled, independ ent of sleep mode. refer to ?analog comparator? on page 194 for details on how to configure the analog comparator. 6.7.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always co nsume power. in the deeper sleep modes, this w ill contribute sig- nificantly to the total current consumption. refer to ?brown-out detect ion? on page 53 for details on how to configure the brown-out detector. 6.7.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage refe rence will be disabled and it w ill not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 55 for details on the start-up time. 6.7.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 56 for details on how to configure the watchdog timer. 6.7.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will 48 7734q?avr?02/12 at90pwm81/161 be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?i/o-ports? on page 68 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?didr1 - digital input disable register 1? on page 222 and ?didr0 - digital input disable register 0? on page 202 for details. 6.7.7 on-chip debug system if the on-chip debug system is enabled by ocden fuse and the chip enter sleep mode, the main clock source is enabled, and hence, alwa ys consumes power. in the deeper sleep modes, this will contribute significantly to the total current consumption. 6.8 register description 6.8.1 smcr - sleep mode control register the sleep mode control register contains control bits for power management. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 6-2 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. bit 76543210 ? ? ? ? sm2 sm1 sm0 se smcr read/write rrrrr/wr/wr/wr/w initial value00000000 table 6-2. sleep mode select. sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010power-down 011reserved 100reserved 101reserved 110standby (1) 111reserved 49 7734q?avr?02/12 at90pwm81/161 6.8.2 prr - power reduction register ? bit 7 - prpsc2: power reduction psc2 writing a logic one to this bit reduces the consumption of the psc2 by stopping the clock to this module. when waking up the psc2 again, the ps c2 should be re initialized to ensure proper operation. ? bit 6 - reserved ? bit 5 - prpscr: power reduction psc reduced writing a logic one to this bit reduces the consumption of the pscr by stopping the clock to this module. when waking up the pscr again, the pscr should be re initialized to ensure proper operation. ? bit 4 - prtim1: power reduction timer/counter1 writing a logic one to this bit reduces the consumption of the timer/counter1 module. when the timer/counter1 is enabled, operation will continue like befo re the setting of this bit. ? bit 3 - reserved ? bit 2 - prspi: power reduction serial peripheral interface writing a logic one to this bit reduces the consumpt ion of the serial peripheral interface by stop- ping the clock to this module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - reserved ? bit 0 - pradc: power reduction adc writing a logic one to this bit r educes the consumption of the adc by stopping the clock to this module. the adc must be disabled before using this function. the analog comparator cannot use the adc input mux when the clock of adc is stopped. bit 7654 321 0 prpsc2 - prpscr prtim1 - prspi - pradc prr read/write r/w r r/w r/w r r/w r r/w initial value0000 000 0 50 7734q?avr?02/12 at90pwm81/161 7. system control and reset 7.1 system control overview 7.1.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the app lication section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 7-1 on page 51 shows the reset logic. table 7-1 on page 51 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 28 . 7.1.2 reset sources the atmel at90pwm81/161 has four sources of reset: ? power-on reset . the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset . the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. the external reset pin can be disabled in 2 ways: ? by the rstdisbl fuse. in this case , the spi programming is disabled. ? by software using the rstdis bit in mc ucr register. in this case , the spi programming is still active at power up time. ? watchdog reset . the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset . the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 51 7734q?avr?02/12 at90pwm81/161 figure 7-1. reset logic. notes: 1. values are guidelines only. 2. the power-on reset will not work unless the supply voltage has been below v pot (falling). 7.1.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 7-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. table 7-1. reset characteristics (1) . symbol parameter condition minimum typical maximum units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (2) 1.3 2.3 v v rst reset pin threshold voltage 0.2v cc 0.85v cc v t rst minimum pulse width on reset pin 400 ns mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit rstdis 52 7734q?avr?02/12 at90pwm81/161 figure 7-2. mcu start-up, reset tied to v cc . figure 7-3. mcu start-up, reset extended externally. 7.1.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 7-1 on page 51 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 7-4. external reset during operation. v reset time-out i n ter n al reset t tout v pot v rst cc reset time-out i n ter n al reset t tout v pot v rst v cc cc 53 7734q?avr?02/12 at90pwm81/161 7.1.5 brown-out detection at90pwm81/161 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no long er guaranteed. the test is performed using bodlevel = 010 for low operating voltag eand bodlevel = 101 for high operating voltage. 2. values are guidelines only. notes: 1. values are guidelines only. when v cc decreases to a value below the trigger level (v bot- in figure 7-5 on page 54 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 7-5 on page 54 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in table 7-3 . table 7-2. bodlevel fuse coding (1)(2) . bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 forbidden, bod must be enabled 110 1.8 v 101 (default configuration) 2.7 100 3.9 4.3 4.6 011 2.3 010 2.2 001 1.9 000 2.5 2.0 2.9 table 7-3. brown-out characteristics (1) . symbol parameter minimum typical maximum units v hyst brown-out detector hysteresis 70 mv t bod minimum pulse width on brown-out reset 2 s 54 7734q?avr?02/12 at90pwm81/161 figure 7-5. brown-out reset during operation. 7.1.6 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 56 for details on operation of the watchdog timer. figure 7-6. watchdog reset during operation. 7.2 system control registers 7.2.1 mcusr - mcu status register the mcu status register provides information on which reset source caused an mcu reset. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog re set occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. v cc reset time-out i n ter n al reset v bot- v bot + t tout ck cc bit 76543210 ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 55 7734q?avr?02/12 at90pwm81/161 ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 7.2.2 mcucr - mcu control register ? bit 3? rstdis: reset pin disable thanks to rstdis in mcucr sfr, the reset func tion can be disabled, leaving this pin for func- tional purpose. ? when the rstdis bit is written to zero, the reset signal is active. ? when the rstdis bit is written to one, the reset signal is inactive. 7.3 internal voltage reference at90pwm81/161 features an internal bandgap reference. this bandgap reference is used for brown-out detection and can be used as analog input for the analog comparators or the adc. the internal voltage reference for the dac and/or the adc and the comparators is derived from this bandgap voltage, see ?on chip voltage reference and temperature sensor overview? on page 189 . the v ref voltage is configured thanks to the refs1 and refs0 bits in the admux register; see ?admux - adc multiplexe r register? on page 217 . 7.3.1 bandgap and internal voltage reference enable signals and start-up time the bandgap and the internal voltage reference characteristics is given on table 7-4 on page 56 . to save power, the reference is not always turned on. the bandgap and the internal refer- ence is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuse). 2. when the internal reference is selected (refs1 = 1). 3. when the bandgap reference is connected to the analog comparator. 4. when the adc is enabled. thus, when the bod is not enabled, after enabling the adc, comparator or the internal refer- ence, the user must always allow the reference to start up before the output from the analog comparator or adc or dac is used. to reduce power consumption in power-down mode, the bit 76543210 ? ? ? pud rstdis ckrc81 ivsel ivce mcucr read/writerrrr/wr/wr/wr/wr/w initial value00000000 56 7734q?avr?02/12 at90pwm81/161 user can avoid the four conditions above to ensur e that the reference is turned off before enter- ing power-down mode. 7.3.2 voltage reference characteristics note: 1. values are guidelines only. 7.4 watchdog timer at90pwm81/161 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separat e on-chip oscillator ? three operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 1ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode figure 7-7. watchdog timer. the watchdog timer (wdt) is a timer counting cy cles of a separate on- chip 128khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the ti me-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. table 7-4. internal voltage reference characteristics (1) . symbol parameter condition mi nimum typical maximum units v bg bandgap reference voltage 1.1 v t bg bandgap reference start-up time 40 s i bg bandgap reference current consumption 15 a 128 khz oscillator mcu reset i n terrupt wdie wdif osc/2k osc/4k osc/8k wdp3 osc/128 osc/1k osc/256 osc/512 57 7734q?avr?02/12 at90pwm81/161 in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent sys tem hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an inter- rupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. the ?watchdog timer always on? (wdton) fuse, if programmed, will fo rce the watchdog timer to system reset mode. with the fuse programmed the system reset mode bit (wde) and inter- rupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the watch- dog timer. the example assumes that interrupt s are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 58 7734q?avr?02/12 at90pwm81/161 note: 1. the example code assumes that the pa rt specific header file is included. note: if the watchdog is accidentally enabled, fo r example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initialisation routine, even if the watchdog is not in use. the following code example shows one assembly and one c function for changing the time-out value of the watchdog timer. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 61 7734q?avr?02/12 at90pwm81/161 . table 7-6. watchdog timer prescaler select. wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0000 2k (2048) cycles 16ms 0001 4k (4096) cycles 32ms 0010 8k (8192) cycles 64ms 0011 16k (16384) cycles 0.125s 0100 32k (32768) cycles 0.25s 0101 64k (65536) cycles 0.5s 0110 128k (131072) cycles 1.0s 0111 256k (262144) cycles 2.0s 1000 512k (524288) cycles 4.0s 1001 1024k (1048576) cycles 8.0s 1010 1k (1024) cycles 8ms 1011 512 cycles 4ms 1100 256 cycles 2ms 1101 128 cycles 1ms 1110 reserved 1111 62 7734q?avr?02/12 at90pwm81/161 8. interrupts this section describes the specifics of t he interrupt handling as performed in the atmel at90pwm81/161. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 13 . 8.1 interrupt vectors in at90pwm81/161 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 233 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vect or will then be the address in this table added to the start address of the boot flash section. table 8-2 on page 63 shows reset and interrupt vectors placement for the various combinations of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also table 8-1. reset and interrupt vectors. vector no. at90pwm81 program address at90pwm161 program address source interrupt definition 1 0x0000 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset, and emulation avr reset 2 0x0001 0x0002 psc2 capt psc2 capture event 3 0x0002 0x0004 psc2 ec psc2 end cycle 4 0x0003 0x0006 psc2 eec psc2 end of enhanced cycle 5 0x0004 0x0008 pscr capt psc reduced capture event 6 0x0005 0x000a pscr ec psc reduced end cycle 7 0x0006 0x000c pscr eec psc reduced end of enhanced cycle 8 0x0007 0x000e anacomp 0 analog comparator 0 9 0x0008 0x0010 anacomp 1 analog comparator 1 10 0x0009 0x0012 anacomp 2 analog comparator 2 11 0x000a 0x0014 int0 external interrupt request 0 12 0x000b 0x0016 timer1 capt timer/counter1 capture event 13 0x000c 0x0018 timer1 ovf timer/counter1 overflow 14 0x000d 0x001a adc adc conversion complete 15 0x000e 0x001c int1 external interrupt request 1 16 0x000f 0x001e spi, stc spi serial transfer complete 17 0x0010 0x0020 int2 external interrupt request 2 18 0x0011 0x0022 wdt watchdog time-out interrupt 19 0x0012 0x0024 ee ready eeprom ready 20 0x0013 0x0026 spm ready store program memory ready 63 7734q?avr?02/12 at90pwm81/161 the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 20-7 on page 246 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in at90pwm81 is: (for at90pwm161, interrupt vector address have an increment equal to 2 in place of 1 for at90pwm81) address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp psc2_capt ; psc2 capture event handler 0x002 rjmp psc2_ec ; psc2 end cycle handler 0x003 rjmp psc2_eec ; psc2 end enhanced cycle handler 0x004 rjmp pscr_capt ; pscr capture event handler 0x005 rjmp pscr_ec ; psc0 end cycle handler 0x006 rjmp pscr_eec ; pscr end enhanced cycle handler 0x007 rjmp ana_comp_0 ; analog comparator 0 handler 0x008 rjmp ana_comp_1 ; analog comparator 1 handler 0x009 rjmp ana_comp_2 ; analog comparator 2 handler 0x00a rjmp ext_int0 ; irq0 handler 0x00b rjmp tim1_capt ; timer1 capture handler 0x00c rjmp tim1_ovf ; timer1 overflow handler 0x00d rjmp adc ; adc conversion complete handler 0x00e rjmp ext_int1 ; irq1 handler 0x00f rjmp spi_stc ; spi transfer complete handler 0x010 rjmp ext_int2 ; irq2 handler 0x011 rjmp wdt ; watchdog timer handler 0x012 rjmp ee_rdy ; eeprom ready handler 0x013 rjmp spm_rdy ; store program memory ready handler 0x014 rjmp 0x015 rjmp 0x016 rjmp 0x017 rjmp 0x018 rjmp 0x019 rjmp 0x01a rjmp 0x01b rjmp table 8-2. reset and interrupt vectors placement in at90pwm81/161 (1) . bootrst ivsel reset address interrupt vectors start address 1 0 0x000 0x001 1 1 0x000 boot reset address + 0x001 0 0 boot reset address 0x001 0 1 boot reset address boot reset address + 0x001 64 7734q?avr?02/12 at90pwm81/161 0x01c rjmp 0x01f rjmp ; 0x020reset: ldi r16, high(ramend); main program start 0x021 out sph,r16 ; set stack pointer to top of ram 0x022 ldi r16, low(ramend) 0x023 out spl,r16 0x024 sei ; enable interrupts 0x025 65 7734q?avr?02/12 at90pwm81/161 for at90pwm161 .org 0x001 0x002 rjmp psc2_capt ; psc2 capture event handler 0x004 rjmp psc2_ec ; psc2 end cycle handler ... ... ... ; 0x03f rjmp spm_rdy ; store program memory ready handler ; .org 0xc00 0xc00 reset: ldi r16,high(ramend); main program start 0xc01 out sph,r16 ; set stack pointer to top of ram 0xc02 ldi r16,low(ramend) 0xc03 out spl,r16 0xc04 sei ; enable interrupts 0xc05 66 7734q?avr?02/12 at90pwm81/161 8.1.2 mcucr - mcu control register ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are pl aced at the star t of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self-programming? on page 233 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired valu e to ivsel while writing a zero to ivce. interrupts will automatically be di sabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabl ed until after the instru ction following the write to ivsel. if ivsel is not written, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is programmed, interrupts are disabled while executing from the a pplication section. if interrupt vectors are placed in the application section and boot lock bit blb 12 is programed, interrupts are disabled while executing from the boot loader section. refer to the section ?boot loader support ? read-while- write self-programming? on page 233 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cyc les after it is written or when ivsel is written. sett ing the ivce bit will disable interrupts, as explained in the ivsel description above. see code example next page. bit 76543210 ? ? ? pud rstdis ckrc81 ivsel ivce mcucr read/writerrrr/wr/wr/wr/wr/w initial value00000000 67 7734q?avr?02/12 at90pwm81/161 assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 69 7734q?avr?02/12 at90pwm81/161 9.2 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 9-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 9-2. general digital i/o (1) . note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 9.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o-ports? on page 81 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 70 7734q?avr?02/12 at90pwm81/161 if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 9.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedant enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 9-1 summarizes the control signals for the pin value. 9.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 9-2 on page 69 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to av oid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 9-3 on page 71 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t p d,max and t p d,min respectively. table 9-1. port pin configurations. ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 71 7734q?avr?02/12 at90pwm81/161 figure 9-3. synchronization when reading an externally applied pin value. consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows t p d,max and t p d,min , a single signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 9-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay t p d through the synchronizer is 1 system clock period. figure 9-4. synchronization when reading a software assigned pin value. the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously di scussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 72 7734q?avr?02/12 at90pwm81/161 note: 1. for the assembly program, two temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 9.2.5 digital input enable and sleep modes as shown in figure 9-2 on page 69 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mcu sleep control- ler in power-down mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 73 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 74 7734q?avr?02/12 at90pwm81/161 the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description table 9-2 for further details. 9.3.1 mcucr - mcu control register table 9-2. generic description of overriding signals for alternate functions. signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardle ss of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, t he port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure 9-5 on page 73 , the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. bit 7 6 5 4 3 2 1 0 ? ? ?pud rstdis ckrc81 ivsel ivce mcucr read/write r r r r/w rw r/w r/w r/w initial value 0 0 0 0 0 0 0 0 75 7734q?avr?02/12 at90pwm81/161 ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 69 for more details about this feature. 9.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 9-3 . the alternate pin configuration is as follows: ? pscout22/icp1/adc9 ? bit 7 pscout22: output 2 of psc 2 icp1 ? input capture pin1: this pin can act as an input capture pin for timer/counter1. adc9: analog to digital converter, input channel 9 . ? miso/acmp3/adc8? bit 6 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input r egardless of the setting of ddb6. when the spi is enabled as a slave, the data direction of this pi n is controlled by ddb6. when the pin is forced to be an input, the pull-up can still be controlled by the portb6 and pud bits. acmp3: analog comparator 3 positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. adc8: analog to digital converter, input channel 8 . table 9-3. port b pins alternate functions. port pin alternate functions pb7 pscout22 output icp1 (timer/counter1 input capture pin ) adc9 (analog input channel 9) pb6 miso (spi master in slave out) acmp3 (analog comparator 3 positive input ) adc8 (analog input channel 8) pb5 adc5 (analog input channel 5) acmp2 (analog comparator 2 positive input) int1(external interrupt 1 input) sck (spi clock) pb4 mosi (spi master out slave in) adc3 (analog input channel 3) acmpm reference for analog comparators pb3 pscoutr1 output adc2 (analog input channel 2) acmp2m (analog comparator 2 negative input) pb2 int0 (external interrupt 0 input) pscout21 output pb1 pscout20 output pb0 t1 counter source pscout23 output acmp3_out( analog comparator3 output) 76 7734q?avr?02/12 at90pwm81/161 ?adc5/acmp2/int1 /sck ? bit 5 adc5: analog to digital converter, input channel 5 . acmp2: analog comparator 2 positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. int1: external interrupt source 1. this pin can serve as an external interrupt source to the mcu. sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regar dless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb5. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb5 bit. ? mosi/adc3/acmpm? bit 4 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb4 when the spi is enabled as a master, the data direction of this pi n is controlled by ddb4. when the pin is forced to be an input, the pull-up can still be controlled by the po rtb4 and pud bits. adc3: analog to digital converter, input channel 3. acmpm: analog comparators negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. ? pscoutr1/adc2/acmp2m? bit 3 pscoutr1: output 1 of pscr. adc2: analog to digital converter, input channel 2 . acmp2m: analog comparator 2 negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. ?int0 /pscout21 ? bit 2 int0: external interrupt source 0. this pin can serve as an external interrupt source to the mcu. pscout21: output 1 of psc 2. ? pscout20 ? bit 1 pscout20: output 0 of psc 2. ? t1/pscout23/acmp3_out ? bit 0 t1: timer/counter1 counter source. pscout23: output 3 of psc 2. acmp3_out: analog comparator3 output. 77 7734q?avr?02/12 at90pwm81/161 table 9-4 and table 9-5 relates the alternate functions of port b to the overriding signals shown in figure 9-5 on page 73 . note: 1. if pscen23 : pscout23 else {if ac3en : acmp3out else : ? } table 9-4. overriding signals for alternate functions in pb7..pb4. signal name pb7/pscout22/ icp1/adc9 pb6/miso/ acmp3/adc8 pb5/adc5/ acmp2/int1 /sck pb4/mosi/adc3 /acmpm puoe 0 spe.mstr spe.mstr spe.mstr puov 0 pb6.pud pb5.pud pb4.pud ddoe pscen22 spe.mstr spe.mstr spe.mstr ddov 1 0 0 0 pvoe pscen22 spe.mstr spe.mstr spe.mstr pvov pscout22 miso sck mosi dieoe adc9d adc8d adc5d|in1en adc3d dieov 0 0 in1en 0 di icp1 - int1 - aio adc9 acmp3/adc8 adc5/acmp2 adc3/acmpm table 9-5. overriding signals for alternate functions in pb3..pb0. signal name pb3/pscoutr1/ adc2/acmp2m pb2/int0/pscout21/ adc2/acmp2m pb1/pscout20 pb0/t1/pscout23 /acmp3_out puoe 0 0 0 0 puov 0 0 0 0 ddoe pscen01 pscen21 pscen20 pscen23|ac3en ddov 1 1 1 1 pvoe pscen01 pscen21 pscen20 pscen23|ac3en pvov pscoutr1 pcout21 pcout20 (1) dieoe adc2d in0en - - dieov 0 in0en - - di - int0 - - aio adc2/acmp2m - - - 78 7734q?avr?02/12 at90pwm81/161 the alternate pin configuration is as follows: 9.3.3 alternate functions of port d the port d pins with alternate functions are shown in table 9-6 . the alternate pin configuration is as follows: ? adc10/pscinra ? bit 7 adc10: analog to digital converter, input channel 10. pcsinra: pscr first alternate digital input. ? apm0+ ? bit 6 amp0+: analog differential amplifier 0 positive input channel. ? amp0-/adc7 ? bit 5 amp0-: analog differential amplifier 0 negative input channel. adc7: analog to digital converter, input channel 7 . ? acmp3m/adc4/pscin2a ? bit 4 acmp3m: analog comparator 3 negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. adc4: analog to digital converter, input channel 4. pcsin2a: psc 2 alternate digital input. table 9-6. port d pins alternate functions. port pin alternate function pd7 adc10 (analog input channel 10) pcsinra (pscr first alternate digital input ) pd6 amp0+ (analog differential amplifier 0 input channel ) pd5 amp0- (analog differential amplifier 0 input channel ) adc7 (analog input channel 7) pd4 acmp3m (analog comparator 3 negative input) adc4 (analog input channel 4) pcsin2a (psc 2 digital input) pd3 adc1 (analog input channel 1) acmp2_out (analog comparator 2 output) pd2 adc0 (analog input channel 0) acmp1 (analog comparator 1 positive input) pd1 pscoutr0 output 0 pcsinrb (pscr second al ternate digital input) pd0 acmp3_out_a (analog comparator 2 alternate output) clko ( system clock) ss ( spi slave select) 79 7734q?avr?02/12 at90pwm81/161 ? adc1/acmp2_out, bit 3 adc1: analog to digital converter, input channel 1. acmp2_out: analog comparator 2 output. ?adc0/acmp1, bit 2 adc0: analog to digital converter, input channel 0 . acmp1: analog comparator 1 positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. ? pscoutr0/pscinrb ? bit 1 pscoutr0: output 0 of pscr. pcsinrb: pscr second alternate digital input. ? acmp3_out_a/ss /clko ? bit 0 acmp2_out_a: analog comparator 2 alternate output. ss : slave port select input. when the spi is enab led as a slave, this pin is configured as an input regardless of the setting of dddn. as a slav e, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by dddn. when the pin is forced to be an input, the pull-up can still be controlled by the portdn bit. clko: divided system clock: the divided system clock can be output on this pin. the divided system clock will be output if the ckout fuse is programmed, regardless of the portdn and dddn settings. it will also be output during reset. table 9-7 and table 9-8 on page 80 relates the alternate functions of port d to the overriding signals shown in figure 9-5 on page 73 . table 9-7. overriding signals for alternate functions pd7..pd4. signal name pd7/adc10/ pscinra pd6/apm0+ pd5/amp0-/adc7 pd4/acmp3m/ adc4/pscin2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe adc10d amp0+d adc7d adc4d dieov 0 0 0 0 di pscinra - - pscin2a aio adc10 amp0+ adc7/amp0- adc4/acmp3m 80 7734q?avr?02/12 at90pwm81/161 9.3.4 alternate functions of port e the port e pins with alternate functions are shown in table 9-9 . the alternate pin configuration is as follows: ? aref/adc6, bit 3 aref: analog reference voltage. see table 17-3 on page 218 for the definition of this pin. adc6: analog to digital converter, input channel 6 . this pin can only be used as a digital output pin. it cannot be read as a digital input. ? xtal2/acmp1m/pscinr ? bit 2 xtal2: chip clock oscillator pin 2. used as clock pin for crystal oscillator or low-frequency crystal oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. table 9-8. overriding signals for alternate functions in pd3..pd0. signal name pd3/adc1/ acmp2_out pd2/adc0/ acmp1 pd1/pscoutr0/ pscinrb pd0/acmp3_out/ss / clko puoe 0 0 0 spe.mstr puov 0 0 0 pd0.pud ddoe ace2en 0 pscen00 acmp3d|(spe.mstr ) ddov 1 0 1 ac3en pvoe ac2en 0 pscen00 ac3en pvov acmp2_out 0 pscout00 avcmp3_out dieoe adc1d adc0d 0 0 dieov 0 0 0 0 di - - pscinrb ss aio adc1 adc0/acmp1 - - table 9-9. port e pins alternate functions. port pin alternate function pe3 aref (analog reference voltage) adc6 (analog input channel 6) pe2 xtal2: xtal output acmp1m (analog comparator 1 negative input) pcsinr (pscr digital input) pe1 xtal1: xtal input pcsin2 (psc 2 digital input) acmp1_out (analog comparator 1 output) pe0 reset (reset input) ocd (on chip debug i/o) int2 (external interrupt 2 input) 81 7734q?avr?02/12 at90pwm81/161 acmp1m: analog comparator 1 negative input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the ana- log comparator. pcsinr: pscr digital input. ? xtal1/pscin2/acmp1_out ? bit 1 xtal1: chip clock oscillator pin 1. used for all chip clock sources except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. pcsin2: psc 2 digital input. acmp1_out: analog comparator 1 output. ? reset /ocd/int2 ? bit 0 reset : reset pin: when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to re ly on power-on reset and brown- out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pe0 is used as a reset pin, dde 0, porte0 and pine0 will all read 0. int2: external interrupt source 2. this pin can serve as an external interrupt source to the mcu. table 9-10 relates the alternate functions of port e to the overriding signals shown in figure 9-5 on page 73 . 9.4 register descrip tion for i/o-ports 9.4.1 portb - port b data register table 9-10. overriding signals for alternate functions in pe2..pe0. signal name pe3/aref/adc6 pe2/xtal2/acm p1m/pscinr pe1/xtal1/psci n2/ acmp1_out pe0/reset /ocd/ int2 puoe0000 puov0000 ddoe 0 0 ac1en 0 ddov 0 0 1 0 pvoe 0 0 ac1en 0 pvov 0 0 acmp1_out 0 dieoe 0 acmp1md 0 in2en dieov000in2en di - pscinr pscin2 int2 aio adc6 acmp1m - - bit 76543210 portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 82 7734q?avr?02/12 at90pwm81/161 9.4.2 ddrb - port b da ta direction register 9.4.3 pinb - port b input pins address 9.4.4 portd - port d data register 9.4.5 ddrd - port d data direction registers 9.4.6 pind - port d input pins address 9.4.7 porte - port e data register 9.4.8 ddre - port e data direction register 9.4.9 pine - port e input pins address bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pind7 pind6 pind5 pind4 pi nd3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? ? ? ? ? porte2 porte1 porte0 porte read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 ? ? ? ? ? dde2 dde1 dde0 ddre read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 ? ? ? ? ? pine2 pine1 pine0 pine read/write rrrrrr/wr/wr/w initial value00000n/an/an/a 83 7734q?avr?02/12 at90pwm81/161 10. external interrupts the external interrupts are triggered by the int2:0 pins. observe that, if enabled, the interrupts will trigger even if th e int2:0 pins are configur ed as outputs. this feat ure provides a way of gen- erating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control reg- isters ? eicra (int2:0). when the external interrupt is enabled and is configured as level triggered, the interrupt will tr igger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int2:0 requires the presence of an i/o clock, described in ?clock sys- tems and their distribution? on page 27 . the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. this makes the mcu less sensitive to noise. the changed level is sampled twice by the watchdog oscillator clock. the period of the watchdog oscillator is 1 s (nominal) at 5.0v and 25c. the frequency of the watchdog oscilla- tor is voltage dependent as shown in the ?electrical characteristics (1)? on page 265 . the mcu will wake up if the input has the requ ired level during this sampling or if it is held until the end of the start-up time. the start-up time is defined by the sut fuses as described in ?system clock and clock options? on page 27 . if the level is sa mpled twice by the watchdog oscillator clock but disappears before the end of the star t-up time, the mcu will still wa ke up, but no interrupt will be generated. the required level must be held long enough for the mcu to complete the wake up to trigger the level interrupt. 10.0.1 eicra - external interrupt control register a ? bits 7..0 ? isc21, isc20 ? isc01, isc00: external interrupt 2 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int2:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 10-1 . edges on int3..int0 are registered asynchro- nously.the value on the int2:0 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses t hat last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrup t. if enabled, a level trig gered interrupt will generat e an interrupt request as long as the pin is held low. bit 76543210 - - isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 table 10-1. interrupt sense ccntrol (1) . iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge between two samples of intn generates an interrupt request 1 1 the rising edge between two samples of intn generates an interrupt request 84 7734q?avr?02/12 at90pwm81/161 note: 1. n = 3, 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 10.0.2 eimsk - external interrupt mask register ? bits 2..0 ? int2 ? int0: external interrupt request 3 - 0 enable when an int2 ? int0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control register ? eicra ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activi ty on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 10.0.3 eifr - external interrupt flag register ? bits 2..0 ? intf2 - intf0: external interrupt flags 3 - 0 when an edge or logic change on the int2:0 pin triggers an interrupt request, intf2:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int2:0 in eimsk, are set (one), the mcu will jump to the interrupt vector . the flag is cleared wh en the interr upt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int2:0 are configured as level interrupt. bit 76543210 -----int2int1iint0eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 -----intf2intf1iintf0eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 85 7734q?avr?02/12 at90pwm81/161 11. reduced 16-bit timer/counter1 the 16-bit timer/counter unit allows accurate program execution timing (event management). the main features are: ? clear timer on compare match (auto reload) ? one input capture unit ? input capture noise canceler ? external event counter ? two independent interrupt sources (tov1, icf1) 11.1 overview most register and bit references in this sect ion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, that is, tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 11-1 on page 86 . for the actual placement of i/o pins, refer to table 2-2 on page 6 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit loca- tions are listed in the ?16-bit timer/counter register description? on page 97 . the prtim1 bit in ?power reduction register? on page 46 must be written to zero to enable timer/counter1 module. 86 7734q?avr?02/12 at90pwm81/161 figure 11-1. 16-bit timer/counter block diagram (1) . note: 1. refer to table 2-1 on page 5 for timer/counter1 pin placement and description. 11.1.1 registers the timer/counter (tcnt1), and input capture register (icr1) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 87 . the timer/counter control registers (tccr1a/b) are 8-bit registers and hav e no cpu access restrictions. interrupt requests (abbreviated to int.req. in figure 11-1 ) signals are all visible in the timer interrupt flag register (tifr1). all interr upts are individually masked with the timer interrupt mask register (timsk1). tifr1 and timsk1 are not shown in figure 11-1 . the timer/counter can be clocked internally, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to incre- ment (or decrement) its value. the timer/counte r is inactive when no cl ock source is selected. the output from the clock select logic is referred to as the timer clock (clk t 1 ). the input capture register can capture the timer/ counter value at a given external (edge trig- gered) event on either the input capture pin (icp1). the input capture unit includes a digital filtering unit (noise canceler) for reduci ng the chance of capturing noise spikes. clock select timer/counter data bus icrn tcntn n oise canceler = fi x ed top values edge detector control logic = 0 top bottom count clear tovn (int.req.) icfn (int.req.) tccrnb tn edge detector (ckio ) clk tn icpn ( from analog comparator ouput ) ac1ice 87 7734q?avr?02/12 at90pwm81/161 the top value, or maximum timer/counter value, can in some modes of operation be defined by the icr1 register, or by a set of fixed values. 11.1.2 definitions the following definitions are used extensively throughout the section: 11.2 accessing 16-bit registers the tcnt1, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for tempor ary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clo ck cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ic r1 register. the assign ment is dependent of the mode of operation. 88 7734q?avr?02/12 at90pwm81/161 note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the a ccess outside the interrupt will be corrupted. theref ore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcnt1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt1h,r17 out tcnt1l,r16 ; read tcnt1 into r17:r16 in r16,tcnt1l in r17,tcnt1h ... c code examples (1) unsigned int i; ... /* set tcnt1 to 0x01ff */ tcnt1 = 0x1ff; /* read tcnt1 into i */ i = tcnt1; ... 89 7734q?avr?02/12 at90pwm81/161 the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example (1) tim16_readtcnt1: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt1 into r17:r16 in r16,tcnt1l in r17,tcnt1h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt1( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt1 into i */ i = tcnt1; /* restore global interrupt flag */ sreg = sreg; return i; } 90 7734q?avr?02/12 at90pwm81/161 the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b or icr1 register s can be done by using the same principle. note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. 11.2.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 11.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs12:0) bits located in the timer/counter control register b (tccr1b). assembly code example (1) tim16_writetcnt1: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt1 to r17:r16 out tcnt1h,r17 out tcnt1l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt1( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt1 to i */ tcnt1 = i; /* restore global interrupt flag */ sreg = sreg; } 91 7734q?avr?02/12 at90pwm81/161 11.3.1 external clock source an external clock source applied to the t1/t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the t1/t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 11-2 shows a functional equivalent block diagram of the t1/t0 synchronization and edge detector logic. the registers are clocked at the po sitive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. figure 11-2. t1/t0 pin sampling. the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1/t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk t hat a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. 11.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 11-3 shows a block diagram of the counter and its surroundings. figure 11-3. counter unit block diagram. tn_sync (to clock select logic) edge detector synchronization d q d q le d q tn clk i/o temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear tovn (int.req.) clock select top bottom tn edge detector ( ckio ) clk tn 92 7734q?avr?02/12 at90pwm81/161 signal description (internal signals): count increment tcnt1 by 1. clear clear tcnt1 (set all bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) con- taining the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirect ly accessed by the cpu. when the cpu does an access to the tcnt1h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register va lue when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will gi ve unpredictable results. the s pecial cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t 1 ). the clk t 1 can be generated from an external or internal clock source, selected by the clock select bits (cs12:0). when no clock source is selected (cs12:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t 1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bit (wgm13) located in the timer/counter control registers b ( tccr1b). the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the wgm13 bit. tov1 can be used for generating a cpu interrupt. 11.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp1 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrate d by the block diagram shown in figure 11-4 on page 93 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. 93 7734q?avr?02/12 at90pwm81/161 figure 11-4. input capture unit block diagram. when a change of the logic level (an event) occurs on the input capture pin (icp1), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a captur e is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as the tcnt1 value is copi ed into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. alternatively the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is copied into the high byte temporary regi ster (temp). when the cpu reads the icr1h i/o location it will access the temp register. the icr1 register can only be written when us ing a waveform generation mode that utilizes the icr1 register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgm13) bits must be set before the top value can be written to the icr1 register. when writing the icr1 register the high byte must be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 87 . 11.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (ac1ice) bit in the analog comparator extended control register (ac1econ). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. icfn (int.req.) write icrn (16-bit register) icrnh (8-bit) noise canceler edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icnc ices icpna 94 7734q?avr?02/12 at90pwm81/161 both the input capture pin (icp1) and the analog comparator 1 output (ac1o) inputs are sam- pled using the same technique as for the t1 pin (see figure 11-2 on page 91 ). the edge detector is also identical. however, when t he noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/coun- ter is set in a waveform generation mode that uses icr1 to define top. an input capture can be trigger ed by software by controlling the port of the icp1 pin. 11.5.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in timer/counter control register b (tccr1b). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icr1 register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 11.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr1 register before the nex t event occurs, the icr1 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 11.6 modes of operation the mode of operation, that is, the behavior of the timer/counter and the output compare pins, is defined by the waveform generation mode (wgm1). for detailed timing information refer to ?timer/counter timing diagrams? on page 95 . 11.6.1 normal mode the simplest mode of operation is the normal mode (wgm13:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 become s zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow 95 7734q?avr?02/12 at90pwm81/161 interrupt that automatically clears the tov1 flag, the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt must be used to extend the resolution for the capture unit. 11.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm13 = 1, previous mode 12), the icr1 register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt1) matches the icr1 . the icr1 define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output fre- quency. it also simplifies the operati on of counting external events. the timing diagram for the ctc mode is shown in figure 11-5 . the counter value (tcnt1) increases until a compare match occurs with icr1, and then counter (tcnt1) is cleared. figure 11-5. ctc mode, timing diagram. an interrupt can be generated at each time the counter value reaches the top value by using the icf1 flag . if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to icr1 is lower than the current value of tcnt1, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. as for the normal mode of operation, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 11.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 11-6 on page 96 shows the count sequence close to top in various modes. t cntn icfn interrupt flag set (interrupt on top) 96 7734q?avr?02/12 at90pwm81/161 figure 11-6. timer/counter timing diagram, no prescaling. figure 11-7 shows the count sequence close to max in various modes. figure 11-7. timer/counter timing diagram, no prescaling. tcntn top - 1 top bottom bottom + 1 clk tn (clk i/ o /1) clk i/ o icfn tovn tcntn bottom bottom + 1 clk tn (clk i/ o /1) clk i/ o max-1 max 97 7734q?avr?02/12 at90pwm81/161 11.8 16-bit timer/counter register description 11.8.1 tccr1b - timer/counter1 control register b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. when the ices1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices1 bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the ices1 setting, the counter value is copied into the input capture register (icr1). the event will also set the input capture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved ? bit 3 ? reserved ? bit 2:0 ? cs12:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 11-2 . bit 7654 3 210 icnc1 ices1 - wgm13 - cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ? bit 4 ? wgm13: waveform generation mode see table 11-1 for the modes definition table 11-1. waveform generation mode bit description. mode wgm13 timer/counter mode of operation top tov1 flag set on 0 0 normal 0xffff max 12 1 ctc icr1 max table 11-2. clock select bit description. cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /1 (no prescaling) 010reserved 98 7734q?avr?02/12 at90pwm81/161 if external pin modes are used for the timer/counter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 11.8.2 tcnt1h and tcnt1l - timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l, combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 87. modifying the counter (tcnt1) while the counte r is running introduces a risk of missing a com- pare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. 11.8.3 icr1h and icr1l - input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 87. 011reserved 100reserved 101reserved 1 1 0 external clock source on t1 pin. clock on falling edge 1 1 1 external clock source on t1 pin. clock on rising edge table 11-2. clock select bit description. (continued) cs12 cs11 cs10 description bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/writer/wr/wr/wr/wr/wr/wr/wr/w initial value00000000 bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/writer/wr/wr/wr/wr/wr/wr/wr/w initial value00000000 99 7734q?avr?02/12 at90pwm81/161 11.8.4 timsk1 - timer/counter1 interrupt mask register ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90 pwm81/161, and will alwa ys read as zero. ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector (see table 8-1 on page 62 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3, 2,1 ? res: reserved bits these bits are unused bits in the at90 pwm81/161, and will alwa ys read as zero. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see table 8-1 on page 62 ) is executed when the tov1 flag, located in tifr1, is set. 11.8.5 tifr1 - timer/counter1 interrupt flag register ? bit 7, 6 ? res: reserved bits these bits are unused bits in the at90 pwm81/161, and will alwa ys read as zero. ? bit 5 ? icf1: timer/count er1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture register (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the coun- ter reaches the top value. icf1 is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3, 2,1 ? res: reserved bits ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wg. tov1 is automatically cleared when the timer/c ounter1 overflow interrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 ? ? icie1 ? ? ? ? toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ??icf1????tov1tifr1 read/write r r r/w r r r/w r/w r/w initial value00000000 100 7734q?avr?02/12 at90pwm81/161 12. power stage controller ? (pscn) the power stage controller is a high performance waveform controller. the atmel at90pwm81 includes one psc2 block. 12.1 features ? pwm waveform generation function (two complementary programmable outputs) ? dead time control ? standard mode up to 12 bit resolution ? frequency and pulse width resolution enhancement mode (12 + 4 bits) ? frequency up to 64mhz ? conditional waveform on external even ts (zero crossing, current sensing ...) ? all on chip psc synchronization ? adc synchronization with digital delay register ? input blanking ? overload protection function ? abnormality protection function, emergency input to force all outputs to low level ? center aligned and edge aligned modes synchronization ? fast emergency stop by hardware 12.2 overview many register and bit references in this section are written in general form. ? a lower case ?n? replaces the psc number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, that is, psoc2 for accessing psc 2 synchro and output configuration register and so on. ? a lower case ?x? replaces the psc part , in this case a or b. however, when using the register or bit defines in a program, the precise form must be used, that is, pfrc2a for accessing psc n fault/retrigger 2 a control register and so on. the purpose of a power stage controller (psc) is to control power modules on a board. it has two outputs on pscn and four outputs on psc2. these outputs can be used in various ways: ? ?two outputs? to drive a half bridge (lighting, dc motor ...) ? ?one output? to drive single power transistor (dc/dc converter, pfc, dc motor ...) ? ?four outputs? in the case of psc2 to drive a full bridge (lighting, dc motor ...) each psc has two inputs the purpose of which is to provide means to act directly on the gener- ated waveforms: ? current sensing regulation ? zero crossing retriggering ? demagnetization retriggering ? fault input the psc can be chained and synchronized to prov ide a configuration to drive three half bridges. thanks to this feature it is possible to generate a three phase waveforms for applications such as asynchronous or bldc motor drive. 101 7734q?avr?02/12 at90pwm81/161 12.3 psc description figure 12-1. power stage controller 0 or 1 block diagram. note: n = 0, 1. the principle of the psc is based on the use of a counter (psc counter). this counter is able to count up and count down from and to values stored in registers according to the selected run- ning mode. the psc is seen as two symmetrical entities. one part named part a which generates the output pscoutn0 and the second one named part b which generates the pscoutn1 output. each part a or b has its own psc input module to manage selected input. databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ocrnsa = pcnfn pfrcnb picrn waveform generator a pscoutn0 pa r t b pa r t a pscn in p u t b pscn in p u t a pcnfen pasdlyn 102 7734q?avr?02/12 at90pwm81/161 12.3.1 psc2 distinctive feature figure 12-2. psc2 versus psc1&psc0 block diagram. note: n = 2. psc2 has two supplementary outputs pscout22 and pscout23. thanks to a first selector pscout22 can duplicate pscout20 or pscout21. thanks to a second selector pscout23 can duplicate pscout20 or pscout21. the output matrix is a kind of 2 2 look up table which gives the poss ibility to program the out- put values according to a psc sequence ( see ?output matrix? on page 129 ). 12.3.2 output polarity the polarity ?active high? or ?active low? of the psc outputs is programmable. all the timing dia- grams in the following examples are given in the ?active high? polarity. databus ocrnrb ocrnsb ocrnra = = = psc counter waveform generator b psc input module b psc input module a pscoutn1 pctln pfrcna psocn ocrnsa = pcnfn pfrcnb pom2(psc2 only) picrn waveform generator a pscoutn0 part a part b pscoutn2 pscoutn3 pscn input b pscn input a pos23 pos22 output matrix pcnfen pasdlyn 103 7734q?avr?02/12 at90pwm81/161 12.4 signal description figure 12-3. psc external block view. note: 1. available only for psc2. 2. n = 0, 1 or 2. 12.4.1 input description table 12-1. internal inputs. note: 1. see figure 12-41 on page 132 ocrnrb[11:0] ocrnra[11:0] ocrnsa[11:0] ocrnrb[1 5 :12] ocrnsb[11:0] picrn[11:0] ir q pscn s y nin psci n n analog comparator n output pscoutn0 pscoutn2 s y nout clk 4 12 12 12 12 clk pscoutn1 pscoutn3 12 pscnas y stopout stopin i/o pll (1) (1) (flank width modulation) 2 2 name description type width ocrnrb[11:0] compare value which reset signal on part b (pscoutn1) register 12 bits ocrnsb[11:0] compare value which set signal on part b (pscoutn1) register 12 bits ocrnra[11:0] compare value which reset signal on part a (pscoutn0) register 12 bits ocrnsa[11:0] compare value which set signal on part a (pscoutn0) register 12 bits ocrnrb[15:12] frequency resolution enhancement value (flank width modulation) register 4 bits clk i/o clock input from i/o clock signal clk pll clock input from pll signal synin synchronization in (from adjacent psc) (1) signal stopin stop input (for synchronized mode) signal 104 7734q?avr?02/12 at90pwm81/161 table 12-2. block inputs. 12.4.2 output description table 12-3. block outputs. table 12-4. internal outputs. note: 1. see figure 12-41 on page 132 2. see ?analog synchronization? on page 131 12.5 functional description 12.5.1 waveform cycles the waveform generated by psc can be described as a sequence of two waveforms. the first waveform is relative to pscoutn0 output and part a of psc. the part of this waveform is sub-cycle a in figure 12-4 on page 105 . the second waveform is relative to pscoutn1 output and part b of psc. the part of this wave- form is sub-cycle b in figure 12-4 on page 105 . the complete waveform is ended with the end of sub-cycle b. it means at the end of waveform b. name description type width pscinn input 0 used for retrigger or fault functions signal from 1st a c input 1 used for retrigger or fault functions signal pscinna input 2 used for retrigger or fault functions signal from 2nd a c input 3 used for retrigger or fault functions signal name description type width pscoutn0 psc n output 0 (f rom part a of psc) signal pscoutn1 psc n output 1 (f rom part b of psc) signal pscoutn2 (psc2 only) psc n output 2 (from part a or part b of psc) signal pscoutn3 (psc2 only) psc n output 3 (from part a or part b of psc) signal name description type width synout synchronization output (1) signal picrn [11:0] psc n input capture register counter value at retriggering event register 12 bits irqpscn psc interrupt request : three sources, overflow, fault, and input capture signal pscnasy adc synchronization (+ amplifier syncho.) (2) signal stopout stop output (for synchronized mode) 105 7734q?avr?02/12 at90pwm81/161 figure 12-4. cycle presentation in 1, 2, and 4 ramp mode. figure 12-5. cycle presentation in centered mode. ramps illustrate the output of the psc counter included in the waveform generators. centered mode is like a one ramp mode which count down up and down. notice that the update of a new set of values is done regardless of ramp mode at the top of the last ramp. 12.5.2 running mode description waveforms and length of output signals are determined by time parameters (dt0, ot0, dt1, ot1) and by the running mode. four modes are possible: ? four ramp mode ?two ramp mode ?one ramp mode ? center aligned mode 12.5.2.1 four ramp mode in four ramp mode, each time in a cycle has its own definition. 4 ramp mode 2 ramp mode 1 ramp mode su b -cycle asu b -cycle b psc cycle update ramp a0 ramp a1 ramp b0 ramp b1 ramp a ramp b psc cycle update centered mode 106 7734q?avr?02/12 at90pwm81/161 figure 12-6. pscn0 & pscn1 basic waveforms in four ramp mode. the input clock of psc is given by clkpsc. pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with: on-time 0 = ocrnrah/l 1/fclkpsc on-time 1 = ocrnrbh/l 1/fclkpsc dead-time 0 = (ocrnsah/l + 2) 1/fclkpsc dead-time 1 = (ocrnsbh/l + 2) 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 2 1/fclkpsc. 12.5.2.2 two ramp mode in two ramp mode, the whole cycle is divided in two moments: one moment for pscn0 description with ot0 which gives the time of the whole moment. one moment for pscn1 description with ot1 which gives the time of the whole moment. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 107 7734q?avr?02/12 at90pwm81/161 figure 12-7. pscn0 & pscn1 basic waveforms in two ramp mode. pscoutn0 and pscoutn1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with: on-time 0 = (ocrnrah/l - ocrnsah/l) 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) 1/fclkpsc dead-time 1 = (ocrnsbh/l + 1) 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 1/fclkpsc. 12.5.2.3 one ramp mode in one ramp mode, pscoutn0 and pscoutn1 outputs can overlap each other. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 108 7734q?avr?02/12 at90pwm81/161 figure 12-8. pscn0 & pscn1 basic waveforms in one ramp mode. on-time 0 = (ocrnrah/l - ocrnsah/l) 1/fclkpsc on-time 1 = (ocrnrbh/l - ocrnsbh/l) 1/fclkpsc dead-time 0 = (ocrnsah/l + 1) 1/fclkpsc dead-time 1 = (ocrnsbh/l - ocrnrah/l) 1/fclkpsc note: minimal value for dead-time 0 = 1/fclkpsc. 12.5.2.4 center aligned mode in center aligned mode, the center of pscn00 and pscn01 signals are centered. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 0 109 7734q?avr?02/12 at90pwm81/161 figure 12-9. pscn0 & pscn1 basic waveforms in center aligned mode. on-time 0 = 2 ocrnsah/l 1/fclkpsc on-time 1 = 2 (ocrnrbh/l - ocrnsbh/l + 1) 1/fclkpsc dead-time = (ocrnsbh/l - ocrnsah/l) 1/fclkpsc psc cycle = 2 (ocrnrbh/l + 1) 1/fclkpsc note: minimal value for psc cycle = 2 1/fclkpsc. ocrnrah/l is not used to cont rol psc output waveform timing. nevertheless, it can be useful to adjust adc synchronization (see ?analog synchronization? on page 131 ). figure 12-10. run and stop mechanism in centered mode. note: see ?pctl2 - psc 2 control register? on page 140 (or pctl1 or pctl2). on-time 1 on-time 0 pscoutn0 pscoutn1 psc cycle dead-time on-time 1 dead-time psc counter ocrnrb ocrnsa ocrnsb 0 pscoutn0 psc counter ocrnrb ocrnsa ocrnsb 0 run pscoutn1 110 7734q?avr?02/12 at90pwm81/161 12.5.3 fifty percent waveform configuration when pscoutn0 and pscoutn1 have the same charac teristics, it?s possib le to configure the psc in a fifty percent mode. when the psc is in this configuration, it duplicates the ocrn- sbh/l and ocrnrbh/l registers in ocrnsah/l and ocrnrah/l registers. so it is not necessary to program ocrnsah/l and ocrnrah/l registers. 12.6 update of values the update of psc waveform registers are done in the following way: ? immediately when the psc is stopped ? at the psc end of cycle when the psc is running ? at the psc end of cycle following the required condition when lock or autolock modes are used to avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values can be updated at the same time at the end of the cycle by the psc. the new set of values is calculated by software and the update is initiated by software. figure 12-11. update at the end of complete psc cycle. the software can stop the cycle before the end to update the values and restart a new psc cycle. 12.6.1 value update synchronization new timing values or psc output configurati on can be written during t he psc cycle. thanks to lock and autolock configuration bits, the new whole set of values can be taken into account with the following conditions: ? when autolock configuration is selected, the update of the psc internal registers will be done at the end of the psc cycle following a write in the output compare register rb. the autolock configuration bit is taken into account at the end of the first psc cycle. ? when lock configuration bit is set, there is no update. the update of the psc internal registers will be done at the end of the psc cycle if the lock bit is released to zero. the registers which update is synchronized thanks to lock and autolock are psocn, pom2, ocrnsah/l, ocrnrah/l, ocrnsbh/l and ocrnrbh/l. see these register?s description starting on page 135 . when set, autolock configuration bit prevails over lock configuration bit. see ?pcnf2 - psc 2 configuration register? on page 136. so f tware psc regulation loop calculation writting in psc registers cycle with set i cycle with set i cycle with set i cycle with set i cycle with set j end o f cycle request f or an update 111 7734q?avr?02/12 at90pwm81/161 12.7 enhanced resolution lamp ballast applications need an enhanced resolu tion down to 50hz. the method to improve the normal resolution is based on flank width modulation (also called fractional divider). cycles are grouped into frames of 16 cycles. cycles are modulated by a sequence given by the fractional divider number. the resulting output frequency is the average of the frequencies in the frame. the fractional divider (d) is given by ocrnrb[15:12]. the psc output period is directly equal to the pscoutn0 on time + dead time (ot0+dt0) and pscoutn1 on time + dead time (ot1+dt1 ) values. these values are 12 bits numbers. the frequency adjustment can only be done in steps like the dedicated counters. the step width is defined as the frequency difference between two neighboring psc frequencies. it is possible to apply the flank width modulation (fwm) on rb, rb+ra, sb, sb+sa. the selection is done bit the bits pbfmn0 and pbfmn. according to the ramp mode and the enhanced resolution mode (defined by pbfmn1:0), the fre- quency difference df can take three different values: with k is the number of clk psc period in a psc cycle and is given by the following formula: with f op is the output operating frequency. example, in normal mode, with maximum operating frequency 160khz and f pll = 64mhz, k equals 400. the resulting resolution is delta f equals 64mhz / 400 / 401 = 400hz. in enhanced mode, the output frequency is the average of the frame formed by the 16 consecu- tive cycles. f b1 and f b2 are two neighboring base frequencies. f 0 = f 1 f 1 f 2 ? f psc k ---------- f psc k 1 + ----------- - ? f psc 1 kk 1 + () ------------------- == = f 2 f 1 f 2 ? f psc k ---------- f psc k 2 + ----------- - ? f psc 2 kk 2 + () ------------------- == = k f psc f op ---------- = f average 16 d ? 16 -------------- - f b 1 d 16 ----- - f b 2 + = 112 7734q?avr?02/12 at90pwm81/161 then the frequency resolution is divided by 16. in the example above, the resolution equals 25hz. according to the ramp mode and the enhanced resolution mode (defined by pbfmn1:0), the average frequency deviation df can take three different values: these values are applied according to the running mode and the enhanced resolution mode as per table 12-5 ; it must be noted that, in one and two ramps modes, it is possible to apply the fwm only on pulse width while keeping a constant frequency. table 12-5. frequency deviation with flank width modulation. notes: 1. the modulation is on the pulse width. 12.7.1 frequency distribution the frequency modulation is done by switching two frequencies in a 16 consecutive cycle frame. these two frequencies are f b1 and f b2 where f b1 is the nearest base frequency above the wanted frequency and f b2 is the nearest base frequency below the wanted frequency. the number of f b1 in the frame is (d-16) and the number of f b2 is d. the f b1 and f b2 frequencies are evenly distrib- uted in the frame according to a predefined pattern. this pattern can be as given in the following table or by any other implementation which give an equivalent evenly distribution. at the end of the 15th cycle (numbered 14 on table 12-6 on page 113 ) an interrupt can be gen- erated. this is the case if the bit peoepen (psc n end of enhanced cycle interrupt enable) is set. this allows: ? to modify the modulation only on a new enhanced cycle start ? to extend the enhanced modulation accuracy by software pbfmn1:0 00 01 10 11 running mode rb rb+ra sb sb+sa four ramps df1 df2 df1 df2 two ramps df1 df2 0 (1) 0 one ramp df1 df1 0 0 center aligned df2 df2 df2 df2 f average 16 d ? 16 -------------- - f pll k ---------- d 16 ----- - f pll k 1 + ----------- - + = f average () 0 = f 1 average () f psc d 16 kk 1 + () ------------------------- - = f 2 average () f psc d 8 kk 2 + () ---------------------- - = 113 7734q?avr?02/12 at90pwm81/161 table 12-6. distribution of f b2 in the modulated frame. while ?x? in the table, f b2 prime to f b1 in cycle corresponding cycle. so for each row, a number of fb2 take place of fb1. figure 12-12. resulting frequency versus d. 12.7.2 modes of operation 12.7.2.1 normal mode the simplest mode of operation is the normal mode. see figure 12-6 on page 106 . the active time of pscoutn0 is given by the ot 0 value. the active time of pscoutn1 is given by the ot1 value. both of them are 12 bit values. thanks to dt0 & dt1 to adjust the dead time between pscoutn0 and pscoutn1 active signals. distribution of fb2 in the modulated frame pwm - cycle fractional divider (d) 0123456789101112131415 0 1x 2x x 3xxx 4xxxx 5xxxxx 6 xxx xxx 7 xxxxxxx 8 xxxxxxxx 9 xxxxxxxxx 10 xxxxxxxxxx 11 xxx xxx xxx x x 12 xxx xxx xxx xxx 13 xxxxxxx xxx xxx 14 xxxxxxx xxxxxxx 15 xxxxxxxxxxxxxxx f b1 f b2 d: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f op 114 7734q?avr?02/12 at90pwm81/161 the waveform frequency is defined by the following equation: 12.7.2.2 enhanced mode the enhanced mode uses the previously described method to generate a high resolution fre- quency. figure 12-13 gives an example of fwm with pbfmn1:0 = 00. figure 12-13. enhanced mode, timing diagram. the supplementary step in counting to generate f b2 is added on the pscn0 signal while needed in the frame according to the fractional divider. see table 12-6 on page 113 . the waveform frequency is defined by the following equations: d is the fractional divider factor. the fwm can be applied on different locations within the psc output waveforms as defined per table 12-15 on page 138 . 12.8 psc inputs part a or b of psc has its own system to take into account one psc n internal input. each part a or b is configured by the psc n input a/b control register ( ?pfrcna - psc n input a control register? on page 141 and ?pfrcnb - psc n input b control register? on page 141 ) and the psc n extended configuration register (see section ?pcnf2 - psc 2 configuration register?, page 136 ). the psc input module a is shown in table 12-14 on page 115 . f pscn 1 pscncycle ----------------------------- - = f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ () --------------------------------------------------------------------- = pscoutn0 t1 period pscoutn1 ot0 ot1 dt1 dt0 t2 ot0 ot1+1 dt1 dt0 dt0 f 1 pscn 1 t 1 ----- f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ () --------------------------------------------------------------------- == f 2 pscn 1 t 2 ----- f clk_pscn ot 0 ot 1 dt 0 dt 11 ++++ () ------------------------------------------------------------------------------ == f average d 16 ----- - f 1 pscn 16 d ? 16 -------------- - f 2 pscn + = 115 7734q?avr?02/12 at90pwm81/161 according to psc n input a control register (see ?pfrcna - psc n input a control register? on page 141 ), psc n input a can act as a retrigger or fault input. each part a or b can be triggered by up to four signals as defined per table 12-18 on page 139 and table 12-19 on page 139 . part a of psc has also a blanking module allo wing to cancel unwanted transitions which may appear on the psc n input a during a certain period of time. the blanking start is defined by the bits pasdlkn(2:0) as per table 12-14 on page 138 . the blanking duration is defined by the register pasdlyn. if the bl anking is select ed by the cor- responding pasdlkn(2:0) bit, all transitions which may appears from the blanking start until a time period are ignored. blanking is level sensitive, that is, a pulse star ted in the blanking window and still at active level after the window will generate a valid retriggering event. figure 12-14. psc input module a. psc input module b is shown on table 12-15 on page 116 . according to psc n input b control register (see ?pfrcnb - psc n input b control register? on page 141 ), psc n input b can act as a retrigger or fault input. ac2o: analog comparator output psci n n digital filter piselna0 pfltena paocna input processing (retriggering ...) psc core (counter , wa v e f orm generator , ...) output control 1 0 0 0 0 1 pscoutn0 (pscoutn1) (pscout22) (pscout23) clk psc clk psc pelevna / prfmna3:0 pcaena 4 ac3o: analog comparator output psci n na piselna1 1 0 1 1 psc n input a input blanking pasdl y ocr sb 3 psc start cycle osr sa pasdlkn(2:0) 2 1 blanking start =0 , 4.. 7 n o blanking 116 7734q?avr?02/12 at90pwm81/161 figure 12-15. psc input module b. 12.8.1 psc retrigger behavior versus psc running modes in centered mode, retrigger inputs have no effect. in two ramp or four ramp mode, retrigger inputs a or b cause the end of the corresponding cycle a or b and the beginning of the following cycle b or a. in one ramp mode, retrigger inputs a or b reset the current psc counting to zero. 12.8.2 retrigger pscoutn0 on external event pscoutn0 output can be reset before end of on-time 0 on the change on pscn input a. pscn input a can be configured to do not act or to act on level or edge modes. the polarity of pscn input a is configurable thanks to a sense control block. pscn input a can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. ac2o: analog comparator output psci n n digital filter piselnb0 pfltenb paocnb input processing (retriggering ...) psc core (counter , wa v e f orm generator , ...) output control 1 0 0 0 0 1 pscoutn0 (pscoutn1) (pscout22) (pscout23) clk psc clk psc clk psc pelevnb prfmnb3:0 pcaenb 4 ac3o:analog comparator output psci n na piselnb1 1 0 1 1 psc n input b 117 7734q?avr?02/12 at90pwm81/161 figure 12-16. pscoutn0 retrograde by pscn input a (edge retriggering). note: this example is given in ?input mode 8? in ?2 or 4 ramp mode?. see figure 12-33 on page 126 for details. figure 12-17. pscoutn0 retriggered by pscn input a (level acting). note: this example is given in ?input mode 1? in ?2 or 4 ramp mode?. see figure 12-22 on page 121 for details. 12.8.3 retrigger pscoutn1 on external event pscoutn1 output can be reset before end of on-time 1 on the change on pscn input b. the polarity of pscn input b is configurable thanks to a sense control block. pscn input b can be configured to do not act or to act on level or edge modes. pscn input b can be the output of the analog comparator or the pscinn input. as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a ( f alling edge) pscn input a (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (high le v el) pscn input a (low le v el) 118 7734q?avr?02/12 at90pwm81/161 figure 12-18. pscoutn1 retriggered by pscn input b (edge retriggering). note: this example is given in ?input mode 8? in ?2 or 4 ramp mode?. see figure 12-33 on page 126 for details. figure 12-19. pscoutn1 retriggered by pscn input b (level acting). note: this example is given in ?input mode 1? in ?2 or 4 ramp mode?. see figure 12-22 on page 121 for details. 12.8.3.1 burst generation note: on level mode, it?s possible to use psc to generate burst by using input mode 3 or mode 4 (see figure 12-26 on page 123 and figure 12-27 on page 123 for details). on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 ( f alling edge) pscn input b (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (high le v el) pscn input b (low le v el) 119 7734q?avr?02/12 at90pwm81/161 figure 12-20. burst generation. 12.8.4 psc input configuration the psc input configuration is done by programming bits in configuration registers. 12.8.4.1 filter enable if the ?filter enable? bit is set, a digital filter of four cycles is inserted before evaluation of the sig- nal. the disable of this function is mainly needed for prescaled psc clock sources, where the noise cancellation gives too high latency. important: if the digital filter is active , the level sensitivity is true also with a disturbed psc clock to deactivate the outputs (emergency protecti on of external component). likewise when used as fault input, pscn input a or input b have to go through psc to act on pscoutn0/1/2/3 output. this way needs that clk psc is running. so thanks to psc asynchronous output control bit (paocna/b), pscnin0/1 input can deactivate directly the psc output. notice that in this case, input is still taken into acc ount as usually by input modu le system as soon as clk psc is running. figure 12-21. psc input filtering. 12.8.4.2 signal polarity one can select the active edge (edge modes) or the active level (level modes). see pelevnx bit description in ?pfrcna - psc n input a control register? on page 141 . if pelevnx bit set, the significant edge of pscn input a or b is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low. off pscoutn0 pscoutn1 pscn input a (high le v el) pscn input a (low le v el) burst digital filter 4 x clk psc input module x ouput stage pscoutnx pi n pscn input a or b clk psc psc 120 7734q?avr?02/12 at90pwm81/161 - in 2- or 4-ramp mode, pscn input a is taken into account only during dead-time0 and on- time0 period (respectively dead-time 1 and on-time1 for pscn input b). - in 1-ramp-mode psc input a or psc input b act on the whole ramp. 12.8.4.3 input mode operation thanks to 4 configuration bits (prfm3:0), it?s possible to define the mode of the psc input. thanks to four configuration bits (prfm3:0), it is possible to define all the modes of the pscr input. these modes are listed in table 12-7 . note: all following examples are given with rising edge or high level active inputs. table 12-7. psc input mode operation. prfm3:0 description 0 0000b pscn input has no action on psc output 1 0001b see ?psc input mode 1: stop signal, jump to opposite dead-time and wait? on page 121. 2 0010b see ?psc input mode 2: stop signal, execute opposite pulse and wait? on page 122. 3 0011b see ?psc input mode 3: stop signal, execute opposite pulse while fault active? on page 123. 4 0100b see ?psc input mode 4: deactivate outputs without changing timing? on page 124. 5 0101b see ?psc input mode 5: stop signal and insert dead-time? on page 124. 6 0110b see ?psc input mode 6: stop signal, jump to opposite dead-time and wait? on page 125. 7 0111b see ?psc input mode 7: halt psc and wait for software action? on page 125. 8 1000b see ?psc input mode 8: edge retrigger psc? on page 126. 9 1001b see ?psc input mode 9: fixed frequency edge retrigger psc? on page 127. 10 1010b reserved: do not use 11 1011b 12 1100b 13 1101b 14 1110b see ?psc input mode 14: fixed frequency edge retrigger psc and deactivate output? on page 128. 15 1111b reserved: do not use 121 7734q?avr?02/12 at90pwm81/161 12.9 psc input mode 1: stop signal, jump to op posite dead-time and wait figure 12-22. pscn behavior versus pscn input a in fault mode 1. psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, waits fo r psc input a inactive state and then jumps and executes dt1 plus ot1. figure 12-23. pscn behavior versus pscn input b in fault mode 1. psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscoutn1, waits fo r psc input b inactive state and then jumps and executes dt0 plus ot0. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 122 7734q?avr?02/12 at90pwm81/161 12.10 psc input mode 2: stop signal, execute opposite pulse and wait figure 12-24. pscn behavior versus pscn input a in fault mode 2. psc input a is take into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscn input a event occurs, psc releas es pscoutn0, jumps and executes dt1 plus ot1 and then waits for psc input a inactive state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com- pletely executed. figure 12-25. pscn behavior versus pscn input b in fault mode 2. psc input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscoutn1, jumps and executes dt0 plus ot0 and then waits for psc input b inactive state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com- pletely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 123 7734q?avr?02/12 at90pwm81/161 12.11 psc input mode 3: st op signal, execute opposite pulse wh ile fault active figure 12-26. pscn behavior versus pscn input a in mode 3. psc input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when psc input a event occurs, psc releases pscoutn0, jumps and executes dt1 plus ot1 plus dt0 while psc input a is in active state. even if psc input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com- pletely executed. figure 12-27. pscn behavior versus pscn input b in mode 3. psc input b is taken into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when psc input b event occurs, psc releases pscnout1, jumps and executes dt0 plus ot0 plus dt1 while psc input b is in active state. even if psc input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com- pletely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 ot1 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 124 7734q?avr?02/12 at90pwm81/161 12.12 psc input mode 4: deactivate outputs without changing timing figure 12-28. psc behavior versus pscn input a or input b in mode 4. figure 12-29. psc behavior versus pscn input a or input b in fault mode 4. pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on- time1/dead-time1. 12.13 psc input mode 5: stop signal and insert dead-time figure 12-30. psc behavior versus pscn input a in fault mode 5. used in fault mode 5, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 pscn input a or pscn input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 dt1 dt0 dt0 pscn input a or pscn input b dt0 dt1 125 7734q?avr?02/12 at90pwm81/161 12.14 psc input mode 6: stop signal, jump to opposite dead-time and wait figure 12-31. psc behavior versus pscn input a in fault mode 6. used in fault mode 6, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. 12.15 psc input mode 7: halt psc and wait for software action figure 12-32. psc behavior versus pscn input a in fault mode 7. note: 1. software action is the setting of the prunn bit in pctln register. used in fault mode 7, pscn input a or pscn input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 so f tware action (1) pscn input a or pscn input b 126 7734q?avr?02/12 at90pwm81/161 12.16 psc input mode 8: edge retrigger psc figure 12-33. psc behavior versus pscn input a in mode 8. the output frequency is modulated by the occurrence of significative edge of retriggering input. figure 12-34. psc behavior versus pscn input b in mode 8. the output frequency is modulated by the occurrence of significative edge of retriggering input. the retrigger event is taken into account only if it occurs during the corresponding on-time. note: in one ramp mode, the retrigger event on input a resets the whole ramp. so the psc doesn?t jump to the opposite dead-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b pscn input b or 127 7734q?avr?02/12 at90pwm81/161 12.17 psc input mode 9: fixed frequency edge retrigger psc figure 12-35. psc behavior versus pscn input a in mode 9. the output frequency is not modified by the occurrence of significative edge of retriggering input. only the output is deactivated when significative edge on retriggering input occurs. note: in this mode the output of the psc becomes active during the next ramp even if the retrig- ger/fault input is active. only the significative edge of retrigger/fault input is taken into account. figure 12-36. psc behavior versus pscn input b in mode 9. the retrigger event is taken into account only if it occurs during the corresponding on-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b 128 7734q?avr?02/12 at90pwm81/161 12.18 psc input mode 14: fixed frequency edge retr igger psc and deactivate output figure 12-37. psc behavior versus pscn input a in mode 14. the output frequency is not modified by the occurrence of significative edge of retriggering input. figure 12-38. psc behavior versus pscn input b in mode 14. the output is deactivated while retriggering input is active. the output of the psc is set to an inactive state and the corresponding ramp is not aborted. the output stays in an inactive state while the retrigger/fault input is active. the psc runs at con- stant frequency. 12.18.1 available input mode according to running mode some input modes are not consistent with some running modes. table 12-8 gives the input modes which are valid according to running modes. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot 0 dt1 ot 1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input b table 12-8. available input modes according to running modes. input mode number: 1 ramp mode 2 ramp mode 4 ramp mode centered mode 1 valid valid valid do not use 2 do not use valid valid do not use 3 do not use valid valid do not use 4 valid valid valid valid 5 do not use valid valid do not use 6 do not use valid valid do not use 129 7734q?avr?02/12 at90pwm81/161 12.18.2 event capture the psc can capture the value of time (psc counter) when a retrigger event or fault event occurs on psc inputs. this value can be read by software in picrnh/l register. 12.18.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the picr1 register before the next event occurs, the picr1 will be overwritten with a new valu e. in this case the result of the capture will be incorrect. when using the input capture interrupt, the picr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 12.19 psc2 outputs 12.19.1 output matrix psc2 has an output matrix which allow in 4 ramp mode to program a value of pscout20 and pscout21 binary value for each ramp. pscout2m takes the value given in table 12-9. during all corresponding ramp. thanks to the output matrix it is possible to generate all kind of pscout20/pscout21 combination. when output matrix is used, the psc n output polarity popn has no action on the outputs. 7 valid valid valid valid 8 valid valid valid do not use 9 valid valid valid do not use 10 do not use 11 12 13 14 valid valid valid do not use 15 do not use table 12-8. available input modes according to running modes. (continued) input mode number: 1 ramp mode 2 ramp mode 4 ramp mode centered mode table 12-9. output matrix versus ramp number. ramp 0 ramp 1 ramp 2 ramp 3 pscout20 pomv2a0 pomv2a1 pomv2a2 pomv2a3 pscout21 pomv2b0 pomv2b1 pomv2b2 pomv2b3 130 7734q?avr?02/12 at90pwm81/161 12.19.2 pscout22 & pscout23 selectors psc 2 has two supplementary outputs pscout22 and pscout23. according to pos22 a nd pos23 bits in psoc2 register , pscout22 and pscout23 duplicate pscout20 and pscou21. if pos22 bit in psoc2 register is clear, pscout22 duplicates pscout20. if pos22 bit in psoc2 register is set, pscout22 duplicates pscout21. if pos23 bit in psoc2 register is clear, pscout23 duplicates pscout21. if pos23 bit in psoc2 register is set, pscout23 duplicates pscout20. figure 12-39. pscout22 and pscout23 outputs. pscout20 pscout21 wa v e f orm generator a wa v e f orm generator b pscout22 pscout23 pos22 pos23 0 1 1 0 output matri x 131 7734q?avr?02/12 at90pwm81/161 12.20 analog synchronization psc generates a signal to synchronize the sample and hold or the adc start; synchronization is mandatory for measurements. this signal can be selected between all falli ng or rising edge of pscn0 or pscn1 outputs as defined per table 12-11 on page 134 and table 12-12 on page 135 . the signal can be shifted by a digital delay de fined by the register pasdly. the shifting clock can be either clkpsc or clkpsc/4, as described per bit 7, 6, 5? pasdlkn( 2:0): analog synchro- nization output delay or input blanking select on page 137 . figure 12-40. analog synchronization. 12.21 interrupt handling as each psc can be dedicated for one function, each psc has its own interrupt system. list of interrupt sources: ? counter reload (end of on time 1) ? end of enhanced cycle ? psc input event (active edge or at the beginning of level configured event) ? psc mutual synchronization error 00 01 10 11 clkpscn/4 clkpscn pasdlkn(2) pscnasy digital delay pasdlyn psyncn(1:0) ocrnsa match ocrnra match a trig/fault ocrnsb match ocrnrb match b trig/fault clkpscn/2 clkpscn/8 pasdlkn(2:0) 5 4 6 7 0 1 132 7734q?avr?02/12 at90pwm81/161 12.22 psc synchronization note: in at90pwm81/161, this feature is not relevant and prun2, parun2 are stuck at zero. 2 or 3 psc can be synchronized together. in this case, two waveform alignments are possible: ? the waveforms are center aligned in the center aligned mode if master and slaves are all with the same psc period (which is the natural use). ? the waveforms are edge aligned in the 1, 2 or 4 ramp mode figure 12-41. psc run synchronization. if the pscm has its parunn bit set, then it can start at the same time than pscn-1. prunn and parunn bits are located in pctln register. see ?pctl2 - psc 2 control register? on page 140. note: do not set the parunn bits on the three psc at the same time. thanks to this feature, we can for example configure two psc in slave mode (parunn = 1 / prunn = 0) and one psc in ma ster mode (parunm = 0 / prunm = 0). this psc master can start all psc at the same moment (prunm = 1). 12.22.1 fault events in autorun mode to complete this master/slave mechanism, faul t event (input mode 7) is propagated from pscn- 1 to pscn and from pscn to pscn-1. a psc which propagate a run signal to the fo llowing psc stops this psc when the run signal is deactivate. according to the architecture of the psc sync hronization which build a ?daisy-chain on the psc run signal? between the three psc, only the fault event (mode 7) which is able to ?stop? the psc through the prun bits is tran smitted along this daisy-chain. pa ru n 0 pru n 0 run psc0 psc0 pa ru n 1 pru n 1 run psc1 psc1 pa ru n 2 pru n 2 run psc2 psc2 s y 0out s y 0in s y 1in s y 2in s y 1out s y 2out 133 7734q?avr?02/12 at90pwm81/161 a psc which receive its run signal from the prev ious psc transmits its fault signal (if enabled) to this previous psc. so a slave psc propagates its fault events when they are configured and enabled. 12.23 psc clock sources psc must be able to generate high frequency with enhanced resolution. each psc has two clock inputs: ? clk pll from the pll ?clk i/o figure 12-42. clock selection. pclkseln bit in psc n configuration register (p cnfn) is used to select the clock source. ppren1/0 bits in psc n control register (pctln) are used to select the divide factor of the clock. table 12-10. output clock versus selection and prescaler. pclkseln ppren1 ppren0 clkpscn output 000clk i/o 0 0 1 clk i/o / 4 0 1 0 clk i/o / 32 0 1 1 clk i/o / 256 100clk pll 1 0 1 clk pll / 4 1 1 0 clk pll / 32 1 1 1 clk pll / 256 clk clk pscn clk pll i/o ck ck/4 ck/32 ck/256 prescaler ck ppren1/0 00 01 10 11 pclkseln 1 0 134 7734q?avr?02/12 at90pwm81/161 12.24 interrupts this section describes the specifics of the in terrupt handling as performed in at90pwm81/161. 12.24.1 list of interrupt vector each psc provides three interrupt vectors ? pscn ec (end of cycle ): when enabled and when a match with ocrnrb occurs ? pscn eec (end of enhanced cycle ): when enabled and when a match with ocrnrb occurs at the 15 th enhanced cycle ? pscn capt (capture event) : when enabled and one of the two following events occurs: retrigger, capture of the psc counter or synchro error. see ?pim2 - psc2 interrupt mask register? on page 143. 12.25 psc register definition registers are explained for psc0. they are identical for psc1. for psc2 only different registers are described. 12.25.1 psoc2 - psc 2 synchro and output configuration ? bit 7 ? pos23: pscout23 selection (psc2 only) when this bit is clear, pscout23 outputs the waveform generated by waveform generator b. when this bit is set, pscout23 outputs the waveform generated by waveform generator a. ? bit 6 ? pos22: pscout22 selection (psc2 only) when this bit is clear, pscout22 outputs the waveform generated by waveform generator a. when this bit is set, pscout22 outputs the waveform generated by waveform generator b. ? bit 5:4 ? psyncn1:0: synchronization out for adc selection select the polarity and signal sour ce for generating a si gnal which will be sent to the adc for synchronization. bit 7 6543210 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a psoc2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 12-11. synchronization source description in one/two/four ramp modes. psyncn1 psyncn0 description 0 0 send signal on leading edge of pscoutn0 (match with ocrnsa) 01 send signal on trailing edge of pscoutn0 (match with ocrnra or fault/retrigger on part a) 1 0 send signal on leading edge of pscoutn1 (match with ocrnsb) 11 send signal on trailing edge of pscoutn1 (match with ocrnrb or fault/retrigger on part b) 135 7734q?avr?02/12 at90pwm81/161 ? bit 3 ? poen2d: pscout23 ou tput enable (psc2 only) when this bit is clear, second i/o pin affected to pscout23 acts as a standard port. when this bit is set, second i/o pin affected to pscout23 is connected to the psc waveform generator b output and is set and clear according to the psc operation. ? bit 2 ? poennb: psc n out part b output enable when this bit is clear, i/o pin affected to pscoutn1 acts as a standard port. when this bit is set, i/o pin affected to pscoutn1 is connected to the psc waveform generator b output and is set and clear according to the psc operation. ? bit 1 ? poen2c: pscout22 ou tput enable (psc2 only) when this bit is clear, second i/o pin affected to pscout22 acts as a standard port. when this bit is set, second i/o pin affected to pscout22 is connected to the psc waveform generator a output and is set and clear according to the psc operation. ? bit 0 ? poenna: psc n out part a output enable when this bit is clear, i/o pin affected to pscoutn0 acts as a standard port. when this bit is set, i/o pin affected to pscoutn0 is connected to the psc waveform generator a output and is set and clear according to the psc operation. 12.25.2 ocrnsah and ocrnsal - output compare sa register 12.25.3 ocrnrah and ocrnral - output compare ra register table 12-12. synchronization source description in centered mode. psyncn1 psyncn0 description 00 send signal on match with ocrnra (during counting down of psc) the minimum value of ocrnra must be 1 01 send signal on match with ocrnra (during counting up of psc) the minimum value of ocrnra must be 1 1 0 no synchronization signal 1 1 no synchronization signal bit 76543210 ????ocrnsa[11:8] ocrnsah ocrnsa[7:0] ocrnsal read/write wwwwwwww initial value00000000 bit 76543210 ????ocrnra[11:8] ocrnrah ocrnra[7:0] ocrnral read/write wwwwwwww initial value00000000 136 7734q?avr?02/12 at90pwm81/161 12.25.4 ocrnsbh and ocrnsbl - output compare sb register 12.25.5 ocrnrbh and ocrnrbl - output compare rb register note: n = 0 to 2 according to psc number. the output compare registers ra, rb, sa and sb contain a 12-bit value that is continuously compared with the psc counter value. a match can be used to generate an output compare interrupt, or to generate a waveform output on the associated pin. the output compare registers rb contains also a 4-bit value that is used for the flank width modulation. the output compare registers are 16-bit and 12-bit in size. to ensure that both the high and low bytes are written simultaneous ly when the cpu writes to these registers, the access is per- formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. 12.25.6 pcnf2 - psc 2 configuration register the psc n configuration register is used to configure the running mode of the psc. ? bit 7 - pfiftyn: psc n fifty writing this bit to one, set the psc in a fifty percent mode where only ocrnrbh/l and ocrn- sbh/l are used. they are duplicated in ocrnrah/l and ocrnsah/l during the update of ocrnrbh/l. this feature is useful to perform fifty percent waveforms. ? bit 6 - palockn: psc n autolock when this bit is set, the output compare registers ra, sa, sb, the output matrix pom2 and the psc output configuration psocn can be wr itten without disturbing the psc cycles. the update of the psc inter nal registers will be done at the end of the psc cycle if the output com- pare register rb has been the last written. when set, this bit prevails over lock (bit 5). bit 76543210 ????ocrnsb[11:8] ocrnsbh ocrnsb[7:0] ocrnsbl read/write wwwwwwww initial value00000000 bit 76543210 ocrnrb[15:12] ocrnrb[11:8] ocrnrbh ocrnrb[7:0] ocrnrbl read/write wwwwwwww initial value00000000 bit 7 6543210 pfifty2 palock2 plock2 pmode21 pmode20 pop2 pclksel2 pome2 pcnf2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 137 7734q?avr?02/12 at90pwm81/161 ? bit 5 ? plockn: psc n lock when this bit is set, the output compare regi sters ra, rb, sa, sb, the output matrix pom2 and the psc output configuration psocn can be written without distur bing the psc cycles. the update of the psc inte rnal registers will be done if the lock bit is released to zero. ? bit 4:3 ? pmoden1: 0: psc n mode select the mode of psc. ? bit 2 ? popn: psc n output polarity if this bit is cleared, the psc outputs are active low. if this bit is set, the psc outputs are active high. ? bit 1 ? pclkseln: psc n input clock select this bit is used to select between clkpf or clkps clocks. set this bit to select the fast clock input (clkpf). clear this bit to select th e slow clock input (clkps). ? bit 0 ? pome2: psc 2 output matrix enable (psc2 only) set this bit to enable the output matrix feature on psc2 outputs. see ?psc2 outputs? on page 129 . when output matrix is used, the psc n output polarity popn has no action on the outputs. 12.25.7 pcnfe2 - psc 2 extended configuration register the psc n extended configuration register is us ed to configure the running mode of the psc. ? bit 7, 6, 5? pasdlkn(2:0): analog synchronization output delay or input blanking select defines the modes for analog signal synchronization delay or input blanking. table 12-13. psc n mode selection. pmoden1 pmoden0 description 0 0 one ramp mode 01two ramp mode 1 0 four ramp mode 1 1 center aligned mode bit 7 6543210 pasdlkn2 pasdlkn1 pasdlkn0 pbfmn1 pelevna1 pelevnb1 piselna1 piselnb1 pcnfe2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 138 7734q?avr?02/12 at90pwm81/161 ? bit 4- pbfmn1: balance fl ank width modulation, bit 1 defines the flank width modulation, together with pbfmn0 bit in pctln register. note: 1. in one ramp mode, changing sa or sa+bsb also affect on-time; see figure 12-8 on page 108 . ? bit 3? pelevna1: psc n input select for part a together with pelevna0, defines active edge or level on psc part a. table 12-14. analog signal synchronization or input blanking mode selection. pasdlkn2 pasdlkn1 pasdlkn0 description 000no analog signal synchronization delay, no i nput blanking 001 no analog signal synchronization delay, input blanking using psc clock, started on psc end of cycle 010 no analog signal synchronization delay, input blanking using psc clock, started on ocr sa event 011 no analog signal synchronization delay, input blanking using psc clock, started on ocr sb event 100analog signal synchronization delay with psc clock, no input blanking 101analog signal synchronization delay with psc clock /2, no input blanking 110analog signal synchronization delay with psc clock /4, no input blanking 111analog signal synchronization delay with psc clock /8, no input blanking table 12-15. flank width mode selection. pbfmn1 pbfmn0 description 0 0 flank width modulation operates on rb (on-time 1 only) 01 flank width modulation operates on rb + ra (on-time 0 and on- time 1) 1 0 flank width modulation operates on sb (dead-time 1 only) (1) 11 flank width modulation operates on sb +sa (dead-time 0 and dead-time 1) table 12-16. psc edge & level input selection. pelevna1 pelevna0 description 00 the falling edge or low level of selected input generates the significative event for retrigger or fault function 01 the rising edge or high level of selected input generates the significative event for retrigger or fault function 10 the toggle of selected input generates the significative event for retrigger or fault function 11reserved 139 7734q?avr?02/12 at90pwm81/161 ? bit 2? pelevnb1: psc n input select for part b together with pelevnb0, defines active edge or level on psc part b. ? bit 1? piselna1: psc n input select for part a together with piselna0, defines active signal on psc part a. ? bit 0? piselnb1: psc n input select for part b together with piselnb0, defines active signal on psc part b. 12.25.8 pasdlyn - analog sy nchronization delay register the analog synchronization delay register store an 8 bit delay used: ? for the input signal blanking. see section ?psc inputs?, page 114 ? for shifting the pscoutnx edg es and the pscnasy signal. see section ?analog synchronization?, page 131 table 12-17. psc edge & level input selection. pelevnb1 pelevnb0 description 00 the falling edge or low level of selected input generates the significative event for retrigger or fault function 01 the rising edge or high level of selected input generates the significative event for retrigger or fault function 10 the toggle of selected input generates the significative event for retrigger or fault function 11reserved table 12-18. psc trigger & fault input selection. piselna1 piselna0 description 0 0 pscinn 0 1 first analog comparator output 1 0 pscinna 1 1 second analog comparator output table 12-19. psc trigger & fault input selection. piselnb1 piselnb0 description 0 0 pscinn 0 1 first analog comparator output 1 0 pscinna 1 1 second analog comparator output bit 76543210 pa s d ly n[ 7: 0 ] pa sd lyn read/write wwwwwwww initial value00000000 140 7734q?avr?02/12 at90pwm81/161 see also the bit definition section ?bit 7, 6, 5? pasdlkn(2: 0): analog synchronization output delay or input blanking select?, page 137 and section ?bit 5:4 ? psyncn1:0: synchronization out for adc selection?, page 134 . 12.25.9 pctl2 - psc 2 control register ? bit 7:6 ? ppren1:0 : psc n prescaler select this two bits select the psc input clock divi sion factor. all generated waveform will be modified by this factor. ? bit 5 ? pbfmn0: balance flank width modulation bit 0 defines the flank width modulation, together with pbfmn1 bit in pcnfen register. see table 12-15 on page 138 . ? bit 4 ? paocnb: psc n asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscoutn1 and pscout23 outputs. see section ?psc clock sources?, page 133 . ? bit 3 ? paocna: psc n asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscoutn0 and pscout22 outputs. see section ?psc clock sources?, page 133 . ? bit 2 ? parunn: psc n autorun when this bit is set, the psc n starts with pscn-1. that means that psc n starts: ? when prunn bit in pctln register is set, ? or when parunn bit in pctln is set and prunn-1 bit in pctln-1 register is set (or parun0 bit and prun0) ? bit 1 ? pccycn: psc n complete cycle when this bit is set, the psc n completes th e entire waveform cycle before halt operation requested by clearing prunn. this bit is not relevant in slave mode (parunn = 1). ? bit 0 ? prunn: psc n run writing this bit to one starts the psc n. when set, this bit prevails over parunn bit. bit 7 6543210 ppre21 ppre20 pbfm20 paoc2b paoc2a parun2 pccyc2 prun2 pctl2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 table 12-20. psc n prescaler selection. ppren1 ppren0 description 0 0 no divider on psc input clock 0 1 divide the psc input clock by 4 1 0 divide the psc input clock by 16 1 1 divide the psc clock by 64 141 7734q?avr?02/12 at90pwm81/161 12.25.10 pfrcna - psc n input a control register 12.25.11 pfrcnb - psc n input b control register the input control registers are used to configure the 2 psc?s retrigger/fault block a & b. the 2 blocks are identical, so they are configured on the same way. ? bit 7 ? pcaenx: psc n capture enable input part x writing this bit to one enables the capture function when external event occurs on input selected as input for part x (see piselnx1:0 bit in the same register). ? bit 6 ? piselnx0: psc n input select for part x together with piselnx1 in pcnfen register, defines active signal on psc module a. see table 12-18 on page 139 and table 12-19 on page 139 . ? bit 5 ?pelevnx0: psc n edge level selector of input part x together with pelevnx1 n pcnfen register, defines active edge & level on psc part x; see table 12-16 on page 138 and table 12-17 on page 139 . ? bit 4 ? pfltenx: psc n filter enable on input part x setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the retrigger pin is filtered. the filter function requires four successive equal valued samples of the retrigger pin for changing its output. the input capture is therefore delayed by four oscilla tor cycles when the nois e canceler is enabled. ? bit 3:0 ? prfmnx3:0: psc n fault mode these four bits define the mode of operation of the fault or retrigger functions. (see table 12-7 on page 120 for more explanations). bit 7 6543210 pcaena piselna0 pelevna0 pfltena prfmna3 prfmna2 prfmna1 prfmna0 pfrcna read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 bit 7 6543210 pcaenb piselnb0 pelevnb0 pfltenb prfmnb3 prfmnb2 prfmnb1 prfmnb0 pfrcnb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 table 12-21. level sensitivity and fault mode operation. prfmnx3:0 description 0000b no action, psc input is ignored 0001b ?psc input mode 1: stop signal, jump to opposite dead-time and wait?, page 121 0010b ?psc input mode 2: stop signal, execute opposite pulse and wait?, page 122 0011b ?psc input mode 3: stop signal, execute opposite pulse while fault active?, page 123 142 7734q?avr?02/12 at90pwm81/161 12.25.12 picr2h and picr2l - psc 2 input capture register ? bit 7 ? pcstn: psc capt ure software trig bit set this bit to trigger off a capture of the psc c ounter. when reading, if this bit is set it means that the capture operation was triggered by pcstn setting otherwise it means that the capture operation was triggered by a psc input. the input capture is updated with the psc counter value each time an event occurs on the enabled psc input pin (or optionally on the analog comparator output) if the capture function is enabled (bit pcaenx in pfrcnx register is set). the input capture register is 12-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit or 12-bit registers. 12.26 psc2 specific register 12.26.1 pom2 - psc 2 output matrix 0100b ?psc input mode 4: deactivate outputs without changing timing?, page 124 0101b ?psc input mode 5: stop signal and insert dead-time?, page 124 0110b ?psc input mode 6: stop signal, jump to opposite dead-time and wait?, page 125 0111b ?psc input mode 7: halt psc and wait for software action?, page 125 1000b ?psc input mode 8: edge retrigger psc?, page 126 1001b ?psc input mode 9: fixed frequency edge retrigger psc?, page 127 1010b reserved (do not use) 1011b 1100b 1101b 1110b ?psc input mode 14: fixed frequency edge retrigger psc and deactivate output?, page 128 1111b reserved (do not use) table 12-21. level sensitivity and fault mode operation. (continued) prfmnx3:0 description bit 76543210 pcst2???picr2[11:8] picr2h picr2[7:0] picr2l read/write rrrrrrrr initial value00000000 bit 7 6543210 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 pom2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 143 7734q?avr?02/12 at90pwm81/161 ? bit 7 ? pomv2b3: output matrix output b ramp 3 this bit gives the state of the pscout21 (and/or pscout23) during ramp 3. ? bit 6 ? pomv2b2: output matrix output b ramp 2 this bit gives the state of the pscout21 (and/or pscout23) during ramp 2. ? bit 5 ? pomv2b1: output matrix output b ramp 1 this bit gives the state of the pscout21 (and/or pscout23) during ramp 1. ? bit 4 ? pomv2b0: output matrix output b ramp 0 this bit gives the state of the pscout21 (and/or pscout23) during ramp 0. ? bit 3 ? pomv2a3: output matrix output a ramp 3 this bit gives the state of the pscout20 (and/or pscout22) during ramp 3. ? bit 2 ? pomv2a2: output matrix output a ramp 2 this bit gives the state of the pscout20 (and/or pscout22) during ramp 2. ? bit 1 ? pomv2a1: output matrix output a ramp 1 this bit gives the state of the pscout20 (and/or pscout22) during ramp 1. ? bit 0 ? pomv2a0: output matrix output a ramp 0 this bit gives the state of the pscout20 (and/or pscout22) during ramp 0. 12.26.2 pim2 - psc2 interrupt mask register ? bit 5 ? pseien: psc n synchro error interrupt enable when this bit is set, the psein bit (if set) generate an interrupt. ? bit 4 ? pevenb: psc n external event b interrupt enable when this bit is set, an external event which ca n generates a capture from retrigger/fault block b generates also an interrupt. ? bit 3 ? pevena: psc n external event a interrupt enable when this bit is set, an external event which ca n generates a capture from retrigger/fault block a generates also an interrupt. ? bit 1? peoepen: psc n end of enhanced cycle interrupt enable when this bit is set, an interrupt is ge nerated when psc reaches the end of the 15 th psc cycle. this allows to update the psc values in the interrupt routine and to start a new enhanced cycle with the new values at the next psc cycle end. ? bit 0 ? peopen: psc n end of cycle interrupt enable when this bit is set, an interrupt is generated when psc reaches the end of the whole cycle. bit 7 6543210 - - pseie2 peve2b peve2a - peoepe2 peope2 pim2 read/write r r r/w r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0 144 7734q?avr?02/12 at90pwm81/161 12.26.3 pifr2 - psc2 interrupt flag register ? bit 7 ? poacnb: psc n output b activity this bit is set by hardware each time the output pscoutn1 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a psc ou tput doesn?t change due to a frozen external input signal. ? bit 6 ? poacna: psc n output a activity this bit is set by hardware each time the output pscoutn0 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a psc ou tput doesn?t change due to a frozen external input signal. ? bit 5 ? psein: psc n synchro error interrupt this bit is set by hardware when the update (or end of psc cycle) of the pscn configured in auto run (parunn = 1) does not occur at the same time than the pscn-1 whic h has generated the input run signal. (for psc0, pscn-1 is psc2). must be cleared by software by writing a one to its location. this feature is useful to detect that a psc doesn?t run at the same speed or with the same phase than the psc master. ? bit 4 ? pevnb: psc n external event b interrupt this bit is set by hardware when an external ev ent which can generates a capture or a retrigger from retrigger/faul t block b occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (pevenb bit = 0). ? bit 3 ? pevna: psc n external event a interrupt this bit is set by hardware when an external ev ent which can generates a capture or a retrigger from retrigger/faul t block a occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (pevena bit = 0). ? bit 2:1 ? prnn1:0: psc n ramp number memorization of the ramp number when the last pevna or pevnb occurred. bit 7 6543210 poac2b poac2a psei2 pev2b pev2a prn21 prn20 peop2 pifr2 read/write r r r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 145 7734q?avr?02/12 at90pwm81/161 ? bit 0 ? peopn: end of psc n interrupt this bit is set by hardware when psc n achieves its whole cycle. must be cleared by software by writing a one to its location. 12.26.4 psc output behavior during reset for external component safety reason, the state of psc outputs during reset can be pro- grammed by fuses pscrv, pscrrb & psc2rb. these fuses are located in the extended fuse byte: notes: 1. see table 7-2 on page 53 for bodlevel fuse decoding. pscrv gives the state low or high which will be forced on psc outputs selected by psc0rb & psc2rb fuses. if pscrv fuse equals 0 (programmed), the selected psc outputs will be forced to low state. if pscrv fuse equals 1 (u nprogrammed), the selected psc output s will be forced to high state. if pscrrb fuse equals 1 (unprogrammed), pscoutr0 & pscoutr1 keep a standard port behavior. if psc0rb fuse equals 0 (programmed), pscoutr0 & pscoutr1 are forced at reset to low level or high level according to pscrv fuse bit. in this second case, pscoutr0 & pscoutr1 keep the forced state until psoc0 register is written. table 12-22. psc n ramp number description. prnn1 prnn0 description 0 0 the last event which has generated an interrupt occurred during ramp 1 0 1 the last event which has generated an interrupt occurred during ramp 2 1 0 the last event which has generated an interrupt occurred during ramp 3 1 1 the last event which has generated an interrupt occurred during ramp 4 table 12-23. extended low fuse byte. extended fuse byte bit no description default value psc2rb 7 psc2 reset behavior 1 psc2rba 6 psc2 reset behavior for out22 & 23 1 pscrrb 5 psc reduced reset behavior 1 pscrv 4 pscout & pscoutr reset value 1 pscinrb 3 psc & pscr inputs reset behavior 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 0 (programmed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) 146 7734q?avr?02/12 at90pwm81/161 if psc2rb fuse equals 1 (unprogrammed), pscout20 & pscout21 keep a standard port behavior. if psc2rb fuse equals 0 (programmed), pscout20 & pscout21 are forced at reset to low level or high leve l according to pscrv fuse bit. in this second case, pscout20 & pscout21 keep the forced state until psoc2 register is written. if psc2rba fuse equals 1 (unprogrammed), pscout22 & pscout23 keep a standard port behavior. if psc2rba fuse equals 0 (programmed), pscout22 & pscout23 are forced at reset to low level or high leve l according to pscrv fuse bit. in this second case, pscout22 & pscout23 keep the forced state until psoc2 register is written. 12.26.5 psc input behavior during reset for power consumption under reset reason, the state of psc & pscr inputs during reset can be programmed by fuse pscinrb. if pscinrb fuse equals 1 (unprogrammed), psc & pscr input keep a standard port behavior. if pscinrb fuse equals 0 (programmed), psc & pscr input pull-up are forced while the reset is active. affected pins are pscin2, pscinr, pscin2a, pscinra. to prevent any conflict on pd1, this fuse has no effect on pscinrb. 147 7734q?avr?02/12 at90pwm81/161 13. reduced power stage controller ? (pscr) the reduced power stage controller is a high performance waveform controller. 13.1 features ? pwm waveform generation function (two complementary programmable outputs) ? dead time control ? standard mode up to 12-bit resolution ? enhanced resolution up to 16 bits ? frequency up to 64mhz ? conditional waveform on external even ts (zero crossing, current sensing ...) ? adc synchronization ? overload protection function ? abnormality protection function, emergency input to force all outputs to high impedance or in inactive state (fuse configurable) ? fast emergency stop by hardware 13.2 overview many register and bit references in this section are written in general form. ? a lower case ?r? (or ?n? replaces the psc number, in this case 0. however, when using the register or bit defines in a program, the precise form must be used, that is, psoc0 for accessing pscr 0 synchro and output configuration register and so on ? a lower case ?x? replaces the pscr part , in this case a or b. however, when using the register or bit defines in a program, the precise form must be used, that is, pfrc0a for accessing pscr 0 fault/retrigger a control register and so on the purpose of a power stage controller (psc) is to control power modules on a board. it has two outputs. these outputs can be used in various ways: ? ?two outputs? to drive a half bridge (for example, lighting applications) ? ?one output? to drive single power transistor (for example, dc/dc converter, pfc applications) the pscr has two inputs the purpose of which is to provide means to act directly on the gener- ated waveforms: ? current sensing regulation ? zero crossing retriggering ? demagnetization retriggering ? fault input 148 7734q?avr?02/12 at90pwm81/161 13.3 pscr description figure 13-1. power stage controller block diagram. the principle of the pscr is based on the use of a counter (pscr counter). this counter is able to count up and count down from and to values stored in registers according to the selected running mode. the pscr is seen as two symmetrical entities . one part named part a which generates the out- put pscoutr0 and the second one named part b which generates the pscoutr1 output. each part a or b has its own pscr input module to manage selected input. 13.3.1 output polarity the polarity ?active high? or ?active low? of the pscr outputs is programmable. all the timing diagrams in the following examples are given in the ?active high? polarity. databus ocrrrb ocrrsb ocrrra = = = pscr counter waveform gererator b psc input module b psc input module a pscoutr1 pctlr pfrcra psocr ocrrsa = pcnfr pfrcrb picrr waveform gererator a pscoutr0 part b part a pscr input b pscr input a 149 7734q?avr?02/12 at90pwm81/161 13.4 signal description figure 13-2. pscr external block view. 13.4.1 input description table 13-1. internal inputs. ocrrrb[11:0] ocrrra[11:0] ocrrsa[11:0] ocrrsb[11:0] picrr[11:0] ir q pscr psci n r analog comparator output pscoutr0 clk 12 12 12 12 clk pscoutr1 12 pscras y i/o pll 3 name description type width ocrrrb[11:0] compare value which reset si gnal on part b (pscoutr1) register 12 bits ocrrsb[11:0] compare value which set signal on part b (pscoutr1) register 12 bits ocrrra[11:0] compare value which reset si gnal on part a (pscoutr0) register 12 bits ocrrsa[11:0] compare value which set signal on part a (pscoutr0) register 12 bits clk i/o clock input from i/o clock signal clk pll clock input from pll signal 150 7734q?avr?02/12 at90pwm81/161 table 13-2. block inputs. 13.4.2 output description table 13-3. block outputs. table 13-4. internal outputs. 2. see ?analog synchronization? on page 169. name description type width pscinr input 0 used for retrigger or fault functions signal from analog comparator input 1 used for retrigger or fault functions signal pscinra input 2 used for retrigger or fault functions signal pscinrb input 3 used for retrigger or fault functions signal name description type width pscoutr0 pscr output 0 (f rom part a of psc) signal pscoutr1 pscr output 1 (from part b of psc) signal name description type width picrr[11:0] pscr input capture register counter value at retriggering event register 12 bits irqpscr pscr interrupt request: three sources, overflow, fault, and input capture signal pscrasy adc synchronization (+ amplifier synchro.) (2) signal 151 7734q?avr?02/12 at90pwm81/161 13.5 functional description 13.5.1 waveform cycles the waveform generated by pscr can be described as a sequence of two waveforms. the first waveform is relative to pscoutr0 output and part a of psc. the part of this waveform is sub-cycle a in figure 13-3 . the second waveform is relative to pscoutr1 output and part b of psc. the part of this wave- form is sub-cycle b in figure 13-3 . the complete waveform is ended with the end of sub-cycle b. it means at the end of waveform b. figure 13-3. cycle presentation in 1, 2, and 4 ramp mode. ramps illustrate the outp ut of the pscr counter included in the wavefo rm generator s. centered mode is like a one ramp mode which count down up and down. notice that the update of a new set of values is done regardless of ramp mode at the top of the last ramp. 13.5.2 running mode description waveforms and length of output signals are determined by time parameters (dt0, ot0, dt1, ot1) and by the running mode. three modes are possible: ? four ramp mode ?two ramp mode ?one ramp mode the active time of pscoutn0 is given by the ot 0 value. the active time of pscoutn1 is given by the ot1 value. both of them are 12 bit values. thanks to dt0 & dt1 to adjust the dead time between pscoutn0 and pscoutn1 active signals. 4 ramp mode 2 ramp mode 1 ramp mode su b -cycle asu b -cycle b psc cycle update ramp a0 ramp a1 ramp b0 ramp b1 ramp a ramp b 152 7734q?avr?02/12 at90pwm81/161 the waveform frequency is defined by the following equation: 13.5.2.1 four ramp mode in four ramp mode, each time in a cycle has its own definition. figure 13-4. pscr0 & pscr1 basic wavefo rms in four ramp mode. the input clock of pscr is given by clkpsc. pscoutr0 and pscoutr1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with: on-time 0 = ocrrrah/l 1/fclkpsc on-time 1 = ocrrrbh/l 1/fclkpsc dead-time 0 = (ocrrsah/l + 2) 1/fclkpsc dead-time 1 = (ocrrsbh/l + 2) 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 2 1/fclkpsc. f pscn 1 pscncycle ----------------------------- - = f clk_pscn ot 0 ot 1 dt 0 dt 1 +++ () --------------------------------------------------------------------- = on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 153 7734q?avr?02/12 at90pwm81/161 13.5.2.2 two ramp mode in two ramp mode, the whole cycle is divided in two moments: ? one moment for pscr0 description with ot0 which gives the time of the whole moment ? one moment for pscr1 description with ot1 which gives the time of the whole moment figure 13-5. pscr0 & pscr1 basic waveforms in two ramp mode. pscoutr0 and pscoutr1 signals are defined by on-time 0, dead-time 0, on-time 1 and dead-time 1 values with: on-time 0 = (ocrrrah/l - ocrrsah/l) 1/fclkpsc on-time 1 = (ocrrrbh/l - ocrrsbh/l) 1/fclkpsc dead-time 0 = (ocrrsah/l + 1) 1/fclkpsc dead-time 1 = (ocrrsbh/l + 1) 1/fclkpsc note: minimal value for dead-time 0 and dead-time 1 = 1/fclkpsc. 13.5.2.3 one ramp mode in one ramp mode, pscoutr0 and pscoutr1 outputs can overlap each other. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 00 154 7734q?avr?02/12 at90pwm81/161 figure 13-6. pscr0 & pscr1 basic waveforms in one ramp mode. on-time 0 = (ocrrrah/l - ocrrsah/l) 1/fclkpsc on-time 1 = (ocrrrbh/l - ocrrsbh/l) 1/fclkpsc dead-time 0 = (ocrrsah/l + 1) 1/fclkpsc dead-time 1 = (ocrrsbh/l - ocrrrah/l) 1/fclkpsc note: minimal value for dead-time 0 = 1/fclkpsc. 13.5.3 fifty percent waveform configuration when pscoutr0 and pscoutr1 have the same characteristics, it?s possible to configure the pscr in a fifty percent mode. when the pscr is in this configurati on, it duplicates the ocrrsbh/l and ocrrrbh/l registers in ocrrsah/l and ocrrrah/l registers. so it is not necessary to program ocrrsah/l and ocrrrah/l registers. 13.6 update of values the update of pscr waveform registers are done in the following way: ? immediately when the psc is stopped ? at the psc end of cycle when the psc is running ? at the psc end of cycle following the required condition when lock or autolock modes are used to avoid asynchronous and incoherent values in a cycle, if an update of one of several values is necessary, all values are updated at the same time at the end of the cycle by the psc. the new set of values is calculated by software and the update is initiated by software. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 psc cycle ocrnrb ocrnsb ocrnra ocrnsa psc counter 0 155 7734q?avr?02/12 at90pwm81/161 figure 13-7. update at the end of complete pscr cycle. the software can stop the cycle before the end to update the values and restart a new pscr cycle. 13.6.1 value update synchronization new timing values or pscr output configuration can be written during the pscr cycle. thanks to lock and autolock configuration bits, t he new whole set of values can be taken into account with the following conditions: ? when autolock configuration is selected, th e update of the pscr in ternal registers will be done at the end of the pscr cycle following a write in the output compare register rb. the autolock configuration bit is taken into account at the end of the first pscr cycle ? when lock configuration bit is set, there is no update. the update of the pscr internal registers will be done at the en d of the pscr cycle if the lo ck bit is released to zero the registers which update is synchronized th anks to lock and autolock are ocrrsah/l, ocrrrah/l, ocrrsbh/l, ocrrrbh/l and psocr. piselra1 and piselrb1 bits of psocr are immediatly updated in order to behave as piselra0 and piselrb0. see these register?s description starting on page 172 . when set, autolock configuration bit prevails over lock configuration bit. see ?pcnf0 - pscr configuration register? on page 173. 13.7 enhanced resolution the pscr includes the same resolution enhancement as in psc. please see section ?enhanced resolution?, page 111 for the description of this feature. 13.8 pscr inputs each part a or b of pscr has its own system to take into account one pscr input. according to pscr input a/b control register (see description ?pfrc0a - pscr input a control register? on page 175 ), pscrin0/1 input can act has a retrigger or fault input. this system a or b is also configured by th is pscr input a/b control register (pfrcra/b). so f tware psc regulation loop calculation writting in psc registers cycle with set i cycle with set i cycle with set i cycle with set i cycle with set j end o f cycle request f or an update 156 7734q?avr?02/12 at90pwm81/161 figure 13-8. pscr input module. 13.8.1 pscr retrigger behavior versus pscr running modes in two ramp or four ramp mode, retrigger inputs a or b cause the end of the corresponding cycle a or b and the beginning of the following cycle b or a. in one ramp mode, retrigger inputs a or b reset the current pscr counting to zero. 13.8.2 retrigger pscoutr0 on external event pscoutr0 output can be reset before end of on-time 0 on the change on pscr input a. pscr input a can be configured to do not act or to act on level or edge modes. the polarity of pscr input a is configurable thanks to a sense control block. pscr input a can be the output of the analog comparator or the pscinr input. as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. digital filter pfltera (pflterb) paocra (paocrb) input processing (retriggering ...) psc core (counter , wa v e f orm generator , ...) output control 1 0 pscoutr0 (pscoutr1) clk psc clk psc clk psc pelevra / (pelevrb) prfmra3:0 (prfmrb3:0) pcaera (pcaerb) 2 4 ac1o: analog comparator output psci n r piselra0 (piselrb0) 0 0 0 1 psci n ra piselra1 (piselrb1) 1 0 1 1 psci n rb pscr input a (pscr input b) 157 7734q?avr?02/12 at90pwm81/161 figure 13-9. pscoutr0 retriggered by pscr input a (edge retriggering). note: this example is given in ?input mode 8? in ?2 or 4 ramp mode?. see figure 13-26 on page 166 for details. figure 13-10. pscoutr0 retriggered by pscr input a (level acting). note: this example is given in ?input mode 1? in ?2 or 4 ramp mode?. see figure 13-15 on page 161 for details. 13.8.3 retrigger pscoutr1 on external event pscoutr1 output can be reset before end of on-time 1 on the change on pscr input b. the polarity of pscr input b is configurable thanks to a sense control block. pscr input b can be configured to do not act or to act on level or edge modes. pscr input b can be the output of the analog comparator or the pscinr input. on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a ( f alling edge) pscn input a (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input a (high le v el) pscn input a (low le v el) 158 7734q?avr?02/12 at90pwm81/161 as the period of the cycle decreases, the instantaneous frequency of the two outputs increases. figure 13-11. pscoutr1 retriggered by pscr input b (edge retriggering). note: this example is given in ?input mode 8? in ?2 or 4 ramp mode?. see figure 13-26 on page 166 for details. figure 13-12. pscoutr1 retriggered by pscr input b (level acting). note: this example is given in ?input mode 1? in ?2 or 4 ramp mode?. see figure 13-15 on page 161 for details. 13.8.3.1 burst generation note: on level mode, it?s possible to use pscr to generate burst by using input mode 3 or mode 4 ( see figure 13-19 on page 163 and figure 13-20 on page 163 for details.) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 ( f alling edge) pscn input b (rising edge) on-time 0 on-time 1 pscoutn0 pscoutn1 dead-time 1 dead-time 0 pscn input b dead-time 0 (high le v el) pscn input b (low le v el) 159 7734q?avr?02/12 at90pwm81/161 figure 13-13. burst generation. 13.8.4 pscr input configuration the pscr input configuration is done by programming bits in configuration registers. 13.8.4.1 filter enable if the ?filter enable? bit is set, a digital filter of four cycles is inserted before evaluation of the sig- nal. the disable of this function is mainly needed for prescaled pscr clock sources, where the noise cancellation gives too high latency. important: if the digital filter is active, the level sensitivity is true also with a disturbed pscr clock to deactivate the outputs (emergency pr otection of external component). likewise when used as fault input, pscr input a or input b have to go through pscr to act on pscoutr0/1/2/3 output. this way needs that clk pscr is running. so thanks to pscr asynchronous output con- trol bit (paocra/b), pscrin0/1 in put can deactivate directly the pscr output. notice that in this case, input is still taken into account as usua lly by input module system as soon as clk pscr is running. figure 13-14. pscr input filtering. 13.8.4.2 signal polarity one can select the active edge (edge modes) or the active level (level modes). see pelev0x bit description in section ?pfrc0a - pscr input a control register?, page 175 . if pelev0x bit set, the significant edge of pscr input a or b is rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low. off pscoutn0 pscoutn1 pscn input a (high le v el) pscn input a (low le v el) burst digital filter 4 x clk psc input module x ouput stage pscoutnx pi n pscn input a or b clk psc psc 160 7734q?avr?02/12 at90pwm81/161 - in 2- or 4-ramp mode, pscr input a is taken into account only during dead-time0 and on- time0 period (respectively dead-time1 and on-time1 for pscr input b). - in 1-ramp-mode pscr input a or pscr input b act on the whole ramp. 13.8.4.3 input mode operation thanks to four configuration bits (prfm3:0), it is possible to define all the modes of the pscr input. these modes are listed in table 13-5 . note: all the following examples are given with rising edge or high level active inputs. table 13-5. pscr input mode operation. prfm3:0 description 0 0000b pscr input has no action on pscr output 1 0001b see ?pscr input mode 1: stop signal, jump to opposite dead-time and wait? on page 161. 2 0010b see ?pscr input mode 2: stop signal, execute opposite dead-time and wait? on page 162. 3 0011b see ?pscr input mode 3: stop signal, execute opposite while fault active? on page 163. 4 0100b see ?pscr input mode 4: deactivate outputs without changing timing? on page 164. 5 0101b see ?pscr input mode 5: stop signal and insert dead-time? on page 164. 6 0110b see ?pscr input mode 6: stop signal, jump to opposite dead-time and wait? on page 165. 7 0111b see ?pscr input mode 7: halt pscr and wait for software action? on page 165. 8 1000b see ?pscr input mode 8: edge retrigger psc? on page 166. 9 1001b see ?pscr input mode 9: fixed frequency edge retrigger psc? on page 167. 10 1010b reserved: do not use 11 1011b 12 1100b 13 1101b 14 1110b see ?pscr input mode 14: fixed frequency edge retrigger pscr and deactivate output? on page 168. 15 1111b reserved: do not use 161 7734q?avr?02/12 at90pwm81/161 13.9 pscr input mode 1: st op signal, jump to o pposite dead-time and wait figure 13-15. pscr behavior versus pscr input a in fault mode 1. pscr input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscr input a event occurs, pscr releases pscoutr0, waits for pscr input a inactive state and then jumps and executes dt1 plus ot1. figure 13-16. pscr behavior versus pscr input b in fault mode 1. pscr input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when pscr input b event occurs, pscr releases pscoutr1, waits for pscr input b inactive state and then jumps and executes dt0 plus ot0. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 162 7734q?avr?02/12 at90pwm81/161 13.10 pscr input mode 2: stop signal, execute oppos ite dead-time and wait figure 13-17. pscr behavior versus pscr input a in fault mode 2. pscr input a is take into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscr input a event occurs, pscr releases pscoutr0, jumps and executes dt1 plus ot1 and then waits for pscr input a inactive state. even if pscr input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com- pletely executed. figure 13-18. pscr behavior versus pscr input b in fault mode 2. pscr input b is take into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when pscr input b event occurs, pscr releases pscoutr1, jumps and executes dt0 plus ot0 and then waits for pscr input b inactive state. even if pscr input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com- pletely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 163 7734q?avr?02/12 at90pwm81/161 13.11 pscr input mode 3: stop signal, execute oppos ite while fault active figure 13-19. pscr behavior versus pscr input a in mode 3. pscr input a is taken into account during dt0 and ot0 only. it has no effect during dt1 and ot1. when pscr input a event occurs, pscr releases pscoutr0, jumps and executes dt1 plus ot1 plus dt0 while pscr input a is in active state. even if pscr input a is released during dt1 or ot1, dt1 plus ot1 sub-cycle is always com- pletely executed. figure 13-20. pscr behavior versus pscr input b in mode 3. pscr input b is taken into account during dt1 and ot1 only. it has no effect during dt0 and ot0. when pscr input b event occurs, pscr releas es pscoutr1, jumps and executes dt0 plus ot0 plus dt1 while pscr input b is in active state. even if pscr input b is released during dt0 or ot0, dt0 plus ot0 sub-cycle is always com- pletely executed. pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 ot1 dt1 ot1 pscoutn0 pscoutn1 psc input a psc input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 164 7734q?avr?02/12 at90pwm81/161 13.12 pscr input mode 4: deactivat e outputs without changing timing figure 13-21. pscr behavior versus pscr input a or input b in mode 4. figure 13-22. pscr behavior versus pscr input a or input b in fault mode 4. pscr input a or pscr input b act indifferently on on-time0/dead-time0 or on on-time1/dead- time1. 13.13 pscr input mode 5: stop signal and insert dead-time figure 13-23. pscr behavior versus pscr input a in fault mode 5. used in fault mode 5, pscr input a or pscr input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 pscn input a or pscn input b dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt1 dt1 dt0 dt0 pscn input a or pscn input b dt0 dt1 165 7734q?avr?02/12 at90pwm81/161 13.14 pscr input mode 6: st op signal, jump to o pposite dead-time and wait figure 13-24. pscr behavior versus pscr input a in fault mode 6. used in fault mode 6, pscr input a or pscr input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. 13.15 pscr input mode 7: halt ps cr and wait for software action figure 13-25. pscr behavior versus pscr input a in fault mode 7. note: 1. software action is the setting of the prunn bit in pctlr register. used in fault mode 7, pscr input a or pscr input b act indifferently on on-time0/dead-time0 or on on-time1/dead-time1. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a or pscn input b pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 so f tware action (1) pscn input a or pscn input b 166 7734q?avr?02/12 at90pwm81/161 13.16 pscr input mode 8: edge retrigger psc figure 13-26. pscr behavior versus pscr input a in mode 8. the output frequency is modulated by the occurrence of significative edge of retriggering input. figure 13-27. pscr behavior versus pscr input b in mode 8. the output frequency is modulated by the occurrence of significative edge of retriggering input. the retrigger event is taken into account only if it occurs during the corresponding on-time. note: in one ramp mode, the retrigger event on input a resets the whole ramp. so the pscr doesn?t jump to the opposite dead-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b pscn input b or 167 7734q?avr?02/12 at90pwm81/161 13.17 pscr input mode 9: fixed frequency edge retrigger psc figure 13-28. pscr behavior versus pscr input a in mode 9. the output frequency is not modified by the occurrence of significative edge of retriggering input. only the output is deactivated when significative edge on retriggering input occurs. note: in this mode the output of the pscr becomes active during the next ramp even if the retrigger/fault input is active. only the signifi cative edge of retrigger/fault input is taken into account. figure 13-29. pscr behavior versus pscr input b in mode 9. the retrigger event is taken into account only if it occurs during the corresponding on-time. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 pscn input b 168 7734q?avr?02/12 at90pwm81/161 13.18 pscr input mode 14 : fixed frequency edge retrigge r pscr and d eactivate output figure 13-30. pscr behavior versus pscr input a in mode 14. the output frequency is not modified by the occurrence of significative edge of retriggering input. figure 13-31. pscr behavior versus pscr input b in mode 14. the output is deactivated while retriggering input is active. the output of the pscr is set to an inactive state and the corresponding ramp is not aborted. the output stays in an inactive state while the retrigger/fault input is active. the pscr runs at constant frequency. 13.18.1 available input mode according to running mode some input modes are not consistent with some running modes. so table 13-6 gives the input modes which are valid according to running modes. pscoutn0 pscoutn1 dt0 ot0 dt1 ot1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input a pscoutn0 pscoutn1 dt0 ot 0 dt1 ot 1 dt0 ot0 dt0 ot0 dt1 ot1 dt1 ot1 dt0 ot0 dt1 ot1 pscn input b table 13-6. available input modes according to running modes. input mode number: 1 ramp mode 2 ramp mode 4 ramp mode 1 valid valid valid 2 do not use valid valid 3 do not use valid valid 4 valid valid valid 5 do not use valid valid 6 do not use valid valid 7 valid valid valid 8 valid valid valid 9 valid valid valid 169 7734q?avr?02/12 at90pwm81/161 13.18.2 event capture the pscr can capture the value of time (pscr c ounter) when a retrigger event or fault event occurs on pscr inputs. this value can be read by software in picrrh/l register. 13.18.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the picr1 register before the next event occurs, the picr1 will be overwritten with a new valu e. in this case the result of the capture will be incorrect. when using the input capture interrupt, the picr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 13.19 analog synchronization pscr generates a signal to synchronize the sample and hold; synchronization is mandatory for measurements. this signal can be selected between all falling or rising edg e of pscr0 or pscr1 outputs. 13.20 interrupt handling list of interrupt sources: ? counter reload (end of on time 1) ? pscr input event (active edge or at the beginning of level configured event) 13.21 psc clock sources pscr must be able to generate high frequency with enhanced resolution. the pscr has two clock inputs: ? clk pll from the pll ?clk i/o 10 do not use 11 12 13 14 valid valid valid 15 do not use table 13-6. available input modes according to running modes. (continued) input mode number: 1 ramp mode 2 ramp mode 4 ramp mode 170 7734q?avr?02/12 at90pwm81/161 figure 13-32. clock selection. pclkselr bit in pscr configurati on register (pcnfr) is used to select the clock source. pprer1/0 bits in pscr control register (pctlr) are used to select the divide factor of the clock. 13.22 interrupts this section describes the specifics of the in terrupt handling as performed in at90pwm81/161. 13.22.1 list of interrupt vector the pscr provides 3 interrupt vectors: ? psc0ec (end of cycle ): when enabled and when a match with ocrrrb occurs ? psc0eec (end of enhanced cycle ): when enabled and when a match with ocrrrb occurs at the 15th enhanced cycle ? psc0capt (capture event) : when enabled and one of the two following events occurs : retrigger, capture of the pscr counter or synchro error see psc0 interrupt mask register page 177 and psc0 interrupt flag register page 178 . table 13-7. output clock versus selection and prescaler. pclkselr pprer1 pprer0 clkpscr output 000clk i/o 0 0 1 clk i/o / 4 0 1 0 clk i/o / 32 0 1 1 clk i/o / 256 100clk pll 1 0 1 clk pll / 4 1 1 0 clk pll / 32 1 1 1 clk pll / 256 clk clk pscr clk pll i/o ck ck/4 ck/32 ck/256 prescaler ck pprer1/0 00 01 10 11 pclkselr 1 0 171 7734q?avr?02/12 at90pwm81/161 13.23 pscr regist er definition 13.23.1 psoc0 - pscr synchro and output configuration ? bit 7? pisel0a1: psc input select for part a together with pisel0a0, defines active signal on pscr part a. ? bit 6? pisel0b1: pscr input select for part b together with pisel0b0, defines active signal on pscr part b. ? bit 5:4 ? psync01:0: synchr onization out for adc selection) select the polarity and signal sour ce for generating a si gnal which will be sent to the adc for synchronization. ? bit 3 ? reserved ? bit 2 ? poen0b: pscr out part b output enable when this bit is clear, i/o pin affected to pscout01 acts as a standard port. bit 7 6543210 pisel0a1 pisel0b1 psync01 psync00 - poen0b - poen0a psoc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-8. psc trigger & fault input selection. pisel0a1 pisel0a0 description 0 0 pscinr 0 1 analog comparator output 1 0 pscinra 1 1 pscinrb table 13-9. psc trigger & fault input selection. pisel0b1 pisel0b0 description 0 0 pscinr 0 1 analog comparator output 1 0 pscinra 1 1 pscinrb table 13-10. synchronization source description in one/two/four ramp modes. psync01 psync00 description 0 0 send signal on leading edge of pscout00 (match with ocr0sa) 01 send signal on trailing edge of pscout00 (match with ocr0ra or fault/retrigger on part a) 1 0 send signal on leading edge of pscout01 (match with ocr0sb) 11 send signal on trailing edge of pscout01 (match with ocr0rb or fault/retrigger on part b) 172 7734q?avr?02/12 at90pwm81/161 when this bit is set, i/o pin affected to psc out01 is connected to the pscr waveform genera- tor b output and is set and clear according to the pscr operation. ? bit 1 ? reserved ? bit 0 ? poen0a: pscr out part a output enable when this bit is clear, i/o pin affected to pscout00 acts as a standard port. when this bit is set, i/o pin affected to psc out00 is connected to the pscr waveform genera- tor a output and is set and clear according to the pscr operation. 13.23.2 ocr0sah and ocr0sal - output compare sa register 13.23.3 ocr0rah and ocr0ral - output compare ra register 13.23.4 ocr0sbh and ocr0sbl - output compare sb register 13.23.5 ocr0rbh and ocr0rbl - output compare rb register the output compare registers ra, rb, sa and sb contain a 12-bit value that is continuously compared with the pscr counter value. a match can be used to generate an output compare interrupt, or to generate a waveform output on the associated pin. the output compare registers rb contains also a 4-bit value that is used for the flank width modulation. the output compare registers are 12-bit in size. to ensure that both the high and low bytes are written simultaneously when the cp u writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16- bit registers. bit 76543210 ????ocr0sa[11:8] ocr0sah ocr0sa[7:0] ocr0sal read/write wwwwwwww initial value00000000 bit 76543210 ????ocr0ra[11:8] ocr0rah ocr0ra[7:0] ocr0ral read/write wwwwwwww initial value00000000 bit 76543210 ????ocr0sb[11:8] ocr0sbh ocr0sb[7:0] ocr0sbl read/write wwwwwwww initial value00000000 bit 76543210 ocr0rb[15:12] ocr0rb[11:8] ocr0rbh ocr0rb[7:0] ocr0rbl read/write wwwwwwww initial value00000000 173 7734q?avr?02/12 at90pwm81/161 13.23.6 pcnf0 - pscr configuration register ? bit 7 - pfifty0: pscr fifty writing this bit to one, set the pscr in a fifty percent mode where only ocr0rbh/l and ocr0sbh/l are used. they are duplicated in ocr0rah/l and ocr0sah/l during the update of ocr0rbh/l. this feature is useful to perform fifty percent waveforms. ? bit 6 - palock0: pscr autolock when this bit is set, the output compare registers ra, sa, sb, the output matrix pom2 and the pscr output configuration psoc0 can be written without disturbing the pscr cycles. the update of the pscr internal registers will be done at the end of the pscr cycle if the output compare register rb has been the last written. when set, this bit prevails over lock (bit 5). ? bit 5 ? plock0: pscr lock when this bit is set, the output compare regi sters ra, rb, sa, sb, the output matrix pom2 and the pscr output configuration psoc0 can be written without disturbing the pscr cycles. the update of the pscr internal registers will be done if the lo ck bit is released to zero. ? bit 4:3 ? pmode01: 0: pscr mode select the mode of psc. ? bit 2 ? pop0: pscr output polarity if this bit is cleared, the pscr outputs are active low. if this bit is set, the pscr outputs are active high. ? bit 1 ? pclksel0: pscr input clock select this bit is used to select between clkpf or clkps clocks. set this bit to select the fast clock input (clkpf). clear this bit to select th e slow clock input (clkps). ? bit 0 ? reserved bit 7 6543210 pfifty0 palock0 plock0 pmode01 pmode00 pop0 pclksel0 - pcnf0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 table 13-11. pscr mode selection. pmode01 pmode00 description 0 0 one ramp mode 01two ramp mode 1 0 four ramp mode 11reserved 174 7734q?avr?02/12 at90pwm81/161 13.23.7 pctl0 - pscr control register ? bit 7:6 ? ppre01:0 : pscr prescaler select this two bits select the pscr input clock divisi on factor. all generated waveform will be modified by this factor. bit 7 6543210 ppre01 ppre00 pbfm01 paoc0b paoc0a pbfm00 pccyc0 prun0 pctl0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 table 13-12. pscr prescaler selection. ppre01 ppre00 description 0 0 no divider on pscr input clock 0 1 divide the pscr input clock by 4 1 0 divide the pscr input clock by 32 1 1 divide the pscr clock by 256 175 7734q?avr?02/12 at90pwm81/161 ? bit 5- pbfm01: balance fl ank width modulation, bit 1 defines the flank width modulation, together with pbfm00 bit. note: 1. in one ramp mode, changing sa or sa+sb also affect on-time; see figure 13-6 on page 154 . ? bit 4 ? paoc0b: pscr asynchronous output control b when this bit is set, fault input selected to block b can act directly to pscout01 output. see section ?pscr input configuration?, page 159 . ? bit 3 ? paoc0a: pscr asynchronous output control a when this bit is set, fault input selected to block a can act directly to pscout00 output. see section ?pscr input configuration?, page 159 . ? bit 2- pbfm00: balance fl ank width modulation, bit 0 defines the flank width modulation, together with pbfm01 bit. ? bit 1 ? pccyc0: pscr complete cycle when this bit is set, the pscr completes the entire waveform cycle before halt operation requested by clearing prun0. this bit is not relevant in slave mode (parun0 = 1). ? bit 0 ? prun0: pscr run writing this bit to one starts the pscr. when set, this bit prevails over parun0 bit. 13.23.8 pfrc0a - pscr i nput a control register 13.23.9 pfrc0b - pscr i nput b control register the input control registers are used to configure the 2 psc?s retrigger/fault block a & b. the 2 blocks are identical, so they are configured on the same way. table 13-13. flank width mode selection. pbfm01 pbfm00 description 0 0 flank width modulation operates on rb (on-time 1 only) 01 flank width modulation operates on rb + ra (on-time 0 and on- time 1) 1 0 flank width modulation operates on sb (dead-time 1 only) (1) 11 flank width modulation operates on sb +sa (dead-time 0 and dead-time 1) bit 7 6543210 pcae0a pisel0a0 pelev0a pflte0a prfm0a3 prfm0a2 prfm0a1 prfm0a0 pfrc0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 bit 7 6543210 pcae0b pisel0b0 pelev0b pflte0b prfm0b3 prfm0b2 prfm0b1 prfm0b0 pfrc0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0000000 176 7734q?avr?02/12 at90pwm81/161 ? bit 7 ? pcae0x: pscr capture enable input part x writing this bit to one enables the capture function when external event occurs on input selected as input for part x (see pisel0x0 bit in the same register). ? bit 6 ? pisel0x0: pscr input select for part x together with pisel0x1 in psoc0 register, defines active signal on psc module a. see table 13-8 on page 171 and table 13-9 on page 171 . ? bit 5 ?pelev0x: pscr edge le vel selector of input part x when this bit is clear, the falling edge or low le vel of selected input generates the significative event for retrigger or fault function. when this bit is set, the rising edge or high le vel of selected input generates the significative event for retrigger or fault function. ? bit 4 ? pflte0x: pscr filter enable on input part x setting this bit (to one) activates the input capt ure noise canceler. when the noise canceler is activated, the input from the retrigger pin is filtered. the filter function requires four successive equal valued samples of the retrigger pin for changing its output. the input capture is therefore delayed by four oscilla tor cycles when the nois e canceler is enabled. ? bit 3:0 ? prfm0x3:0: pscr fault mode these four bits define the mode of operation of the fault or retrigger functions. (see table 13-5 on page 160 for more explanations). table 13-14. level sensitivity and fault mode operation. prfm0x3:0 description 0000b no action, pscr input is ignored 0001b ?pscr input mode 1: stop signal, jump to opposite dead-time and wait?, page 161 0010b ?pscr input mode 2: stop signal, execute opposite dead-time and wait?, page 162 0011b ?pscr input mode 3: stop signal, execute opposite while fault active?, page 163 0100b ?pscr input mode 4: deactivate outputs without changing timing?, page 164 0101b ?pscr input mode 5: stop signal and insert dead-time?, page 164 0110b ?pscr input mode 6: stop signal, jump to opposite dead-time and wait?, page 165 0111b ?pscr input mode 7: halt pscr and wait for software action?, page 165 1000b ?pscr input mode 8: edge retrigger psc?, page 166 1001b ?pscr input mode 9: fixed frequency edge retrigger psc?, page 167 177 7734q?avr?02/12 at90pwm81/161 13.23.10 picr0h and picr0l - pscr input capture register ? bit 7 ? pcst0: pscr capture software trig bit set this bit to trigger off a capture of the pscr coun ter. when reading, if th is bit is set it means that the capture operation was triggered by pcst0 setting otherwise it means that the capture operation was triggered by a pscr input. the input capture is updated with the pscr counter value each time an event occurs on the enabled pscr input pin (or optionally on the analog comparator output) if the capture function is enabled (bit pcae0x in pfrc0x register is set). the input capture register is 12-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit or 12-bit registers. 13.23.11 pim0 - pscr interrupt mask register ? bit 7- 5 ? reserved ? bit 4 ? peve0b: pscr extern al event b interrupt enable when this bit is set, an external event which ca n generates a capture from retrigger/fault block b generates also an interrupt. ? bit 3 ? peve0a: pscr extern al event a interrupt enable when this bit is set, an external event which ca n generates a capture from retrigger/fault block a generates also an interrupt. ? bit 2 ? reserved 1010b reserved (do not use) 1011b 1100b 1101b 1110b ?pscr input mode 14: fixed frequency edge retrigger pscr and deactivate output?, page 168 1111b reserved (do not use) table 13-14. level sensitivity and fault mode operation. (continued) prfm0x3:0 description bit 76543210 pcst0???picr0[11:8] picr0h picr0[7:0] picr0l read/write rrrrrrrr initial value00000000 bit 7 6543210 - - - peve0b peve0a - peoepe0 peope0 pim0 read/write r r r r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 178 7734q?avr?02/12 at90pwm81/161 ? bit 1? peoepe0: pscr end of enha nced cycle interrupt enable when this bit is set, an interrupt is generated when psc reduced reaches the end of the 15th psc cycle. this allows to update the pscr valu es in the interrupt routine and to start a new enhanced cycle with the new values at the next pscr cycle end. ? bit 0 ? peope0: pscr end of cycle interrupt enable when this bit is set, an interrupt is generated when pscr reaches the end of the whole cycle. 13.23.12 pifr0 - pscr interrupt flag register ? bit 7 ? poac0b: pscr output b activity this bit is set by hardware each time the output pscout01 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a pscr output doesn?t change due to a frozen external input signal. ? bit 6 ? poac0a: pscr output a activity this bit is set by hardware each time the output pscout00 changes from 0 to 1 or from 1 to 0. must be cleared by software by writing a one to its location. this feature is useful to detect that a pscr output doesn?t change due to a freezen external input signal. ? bit 5 ? reserved ? bit 4 ? pev0b: pscr ex ternal event b interrupt this bit is set by hardware when an external ev ent which can generates a capture or a retrigger from retrigger/faul t block b occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (peve0b bit = 0). ? bit 3 ? pev0a: pscr ex ternal event a interrupt this bit is set by hardware when an external ev ent which can generates a capture or a retrigger from retrigger/faul t block a occurs. must be cleared by software by writing a one to its location. this bit can be read even if the corresponding in terrupt is not enabled (peve0a bit = 0). ? bit 2:1 ? prn01:0 : pscr ramp number memorization of the ramp number when the last pev0a or pev0b occurred. bit 7 6543210 poac0b poac0a - pev0b pev0a prn01 prn00 peop0 pifr0 read/write r r r r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 179 7734q?avr?02/12 at90pwm81/161 ? bit 0 ? peop0: end of pscr interrupt this bit is set by hardware when pscr achieves its whole cycle. must be cleared by software by writing a one to its location. table 13-15. pscr ramp number description. prn01 prn00 description 0 0 the last event which has generated an interrupt occurred during ramp 1 0 1 the last event which has generated an interrupt occurred during ramp 2 1 0 the last event which has generated an interrupt occurred during ramp 3 1 1 the last event which has generated an interrupt occurred during ramp 4 180 7734q?avr?02/12 at90pwm81/161 14. serial peripheral interface ? spi: 14.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmissi on interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 14.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the at90pwm81/161 and peripheral device s or between several avr devices. the at90pwm81/161 spi includes the following features. figure 14-1. spi block diagram (1) . note: 1. refer to figure 2-1 on page 3 , and table 9-3 on page 75 for spi pin placement. spi2x spi2x divider /2/4/8/1 6 /32/ 6 4/128 clk io miso mosi sck ss 181 7734q?avr?02/12 at90pwm81/161 the interconnection between master and slave cpus with spi is shown in figure 14-2 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pu lling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte , the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incomi ng byte will be kept in the buffer register for later use. figure 14-2. spi master-slave interconnection. the system is single buffered in the transmit di rection and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. shift e n able 182 7734q?avr?02/12 at90pwm81/161 when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 14-1 . for more details on automatic port overrides, refer to ?alternate port functions? on page 73 . note: 1. see ?alternate functions of port b? on page 75 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by th e actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. for example, if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. table 14-1. spi pin overrides (1) . pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 183 7734q?avr?02/12 at90pwm81/161 note: 1. the example code assumes that the pa rt specific header file is included. the following code examples show how to initialize the spi as a slave and how to perform a simple reception. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 186 7734q?avr?02/12 at90pwm81/161 figure 14-3. spi transfer format with cpha = 0. figure 14-4. spi transfer format with cpha = 1. 14.5 spi registers 14.5.1 spcr - spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi in terrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso cha n ge 0 mosi pi n cha n ge 0 miso pi n sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb f irst (dord = 0) lsb f irst (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso cha n ge 0 mosi pi n cha n ge 0 miso pi n sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb f irst (dord = 0) lsb f irst (dord = 1) bit 76543210 spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 187 7734q?avr?02/12 at90pwm81/161 ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 14-3 on page 186 and figure 14-4 on page 186 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 14-3 on page 186 and figure 14-4 on page 186 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the clk io frequency f clkio is shown in table 14-5 : table 14-3. cpol functionality. cpol leading edge trailing edge 0 rising falling 1 falling rising table 14-4. cpha functionality. cpha leading edge trailing edge 0 sample setup 1 setup sample table 14-5. relationship between sck an d the oscillator frequency. spi2x spr1 spr0 sck frequency 000 f clkio / 4 001 f clkio / 16 010 f clkio / 64 011 f clkio / 128 100 f clkio / 2 101 f clkio / 8 110 f clkio / 32 111 f clkio / 64 188 7734q?avr?02/12 at90pwm81/161 14.5.2 spsr - spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dr iven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at 90pwm81/161 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck freque ncy) will be doubled when the spi is in master mode (see table 14-5 on page 187 ). this means that th e minimum sck period will be two cpu clock periods. when the spi is conf igured as slave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the at90pwm81/161 is also used for program memory and eeprom downloading or uploading. see ?serial programming algorithm? on page 261 for serial program- ming and verification. 14.5.3 spdr - spi data register ? bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit 76543210 spifwcol?????spi2xspsr read/write rrrrrrrr/w initial value00000000 bit 76543210 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxu ndefined 189 7734q?avr?02/12 at90pwm81/161 15. voltage reference and temperature sensor 15.1 features ? accurate voltage reference of 2.56v ? internal temperature sensor ? possibility for runtime compensatio n of temperature drift in both voltage reference and on-chip oscillators ? low power consumption 15.2 on chip voltage reference and temperature sensor overview a low power band-gap reference provides at90pwm81/161 with an accurate on-chip bandgap voltage of 1.100v (vbg). then when sw1 is off and sw2/sw3 is on, the bandgap voltage is multiplied and generates the internal reference v ref of 2.56v. this reference voltage is used as reference for the adc, the dac and can use a buffer with external decoupli ng capacitor (when sw0 is on) to enable excel- lent noise performance with minimum power consumption as shown on figure 15-1 on page 190 . the selection of the voltage reference for all the analog components (adc, dac, compara- tors) is done using the refs1:0 bits in admux register; see ?admux - adc multiplexer register? on page 217 . for conditions using the bandgap and the internal voltage reference, see ?bandgap and internal voltage reference enable signals and start-up time? on page 55 . 190 7734q?avr?02/12 at90pwm81/161 figure 15-1. reference circuitry. at90pwm81/161 has an on-chip temperature sensor for monitoring the die temperature. a volt- age proportional-to-absolute-temperature, vptat, is generated in the voltage reference circuit and after buffering, is connected to the adc multiplexer. this temperature sensor can be used for runtime compensation of temperature drift in both the voltage reference and the on-chip oscillator. to get the absolute temperature in degrees kelvin, the measured vtemp voltage must be scaled with the vtemp factory calibration value stored in the signature row. see section ?temperature measurement?, page 192 for details. vbg and vtemp can be measured with the integrated adc by selecting the proper adc channel with admux (see ?admux - adc multiplexer register? on page 217 ). 15.3 register description 15.3.1 bgccr ? bandgap ca libration current register vptat refs0, refs1 are used to control sw0..3 /3.20 /2.13 /1. 6 0 / 6 .40 vre f voltage re f erence are f avcc v b g adc comp bg re f erence bg cali b ration registers bgccr , bgcrr bg cali b ration fuses sw0 sw1 sw2 sw3 bit 7 6543210 - - - - bgcc3 bgcc2 bgcc1 bgcc0 bgccr read/write - - - - r/w r/w r/w r/w initial value 0 0 0 0 1 0 0 0 191 7734q?avr?02/12 at90pwm81/161 ? bit 7:4 ? res: reserved bit this bit is reserved for future use. ? bit 3:0 ? bgcc3:0: bg calibration of ptat current these bits are used for trimming of the nomina l value of the bandgap reference voltage. these bits are binary coded, so the lowest value for vbg is reached when bgcc3:0 is 0000 and the maximum value when bgcc3:0 is 1111. th e step size is approximately 5mv. updating the bgcc bits will affect the bod detection level. the bod will react quickly to the new detection level. 15.3.2 bgcrr ? bandgap calibration resistor register ? bit 7:4 ? res: reserved bit this bit is reserved for future use. ? bit 3:0 ? bgcr3:0: bg calibration of resistor ladder these bits are used for temperature gradient adjustment of the bandgap reference. figure 15-2 on page 192 illustrates vbg as a function of temperature. vbg has a po sitive temperature coeffi- cient at low temperatures and negative temperature coefficient at high temperatures. depending on the process variations, the top of the vbg curve may be located at higher or lower temperatures. to minimize the temperat ure drift in the temperat ure range of interest, bgcrr is used to adjust the top of the curve towards the centre of the temperature range of interest. the bgcrr bits are thermometer coded, resulting in 5 possible settings: 0000, 0001, 0011, 0111, 1111. the value 0000 shifts the top of the vbg curve to the highest possible temperature, and the value 1111 shifts the top of the vbg curve to the lowest possible temperature. bit 7 6543210 - - - - bgcr3 bgcr2 bgcr1 bgcr0 bgcrr read/write - - - - r/w r/w r/w r/w initial value 0 0 0 0 1 0 0 0 192 7734q?avr?02/12 at90pwm81/161 figure 15-2. illustration of vbg as a function of temperature. 15.4 temperature measurement the temperature measurement is based on an on-ch ip temperature sensor that is coupled to a single ended adc12 channel, as shown on figure 15-3 . figure 15-3. temperature sensor circuitry. selecting the adc12 channel by writing the mux3..0 bits in admux register to ?1100? enables the temperature sensor (see ?admux - adc multiplexe r register? on page 217 ). the recom- mended adc voltage reference source is the internal 2.56v voltage reference for temperature sensor measurement. when the temperature sensor is enabled, the adc converter can be used in single conversion mode to measure the voltage over the temperature sensor. the amplifier allows to charge the adc sample capacitor at full ckadc clock speed. the measured voltage has a linear relationship to temperature as described in table 15-1 on page 193 . when the volt- age reference equals 2.56v, the conversion result has approximately a 1lsb/c (or 2.5mv/c) temperature (c) 1.0 temperature range of interest -20 1.5 0.5 -40 bgcrr is used to move the top of the vbg curve to the center of the temperature range of interest 40 20 -0 100 8 0 60 vptat adc mux=1100 current- v oltage con v ertor bg re f erence enable when aden=1 enable when adc mux=1100 vtemp + - 193 7734q?avr?02/12 at90pwm81/161 correlation to temperature and the typical ac curacy of the temperature measurement is 10c after offset calibration. the values described in table 15-1 are typical values. however, due to the process variation the temperature sensor output voltage varies from one chip to another. to be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. when using temperature sensor, the temperat ure (in kelvin) is calculated as follows: t = a t ptat + b , where a - gain correction multiplier (constant '1', or unsigned fixed point number) b - offset correction term (2. complement signed byte) t ptat - adc result when measuring temperature sensor voltage, v ref with 2.56v internal reference t - temperature in kelvin (k = c + 273) example: if a = 0x80 (=1.00) and b = 8, and adc result is 0x15e (=350), this gives a measured tempera- ture of: t = 1.00 350 + 8 = 358k (+85c) 15.4.1 manufacturing calibration one can also use the calibration values available in the signature row. see ?reading the signa- ture row from software? on page 243 . the calibration values are determined from values measured during test at room temperature which is approximatively +25c. ca libration measures are done at v cc = 3v and with adc in internal v ref (1.1v) mode. the temperature in celsiu s degrees can be calculat ed utilizing the formula: t = ((([(adch << 8) | adcl] -(273 + 25-tsoffset)) tsgain)/128) + 25 where: a. adch & adcl are the adc data registers. b. tsgain is the temperature sensor gain (unsigned fixed point 8-bit temperature sensor gain factor in 1/128th units stored as previously in the signature row at address 0x0007). see ?reading the signature row from software? on page 243 . c. tsoffset is the temperature sensor offset correction term (signed twos complement 7-bit temperature sensor offset reading stored as previously in the signature row at address 0x0005). table 15-1. temperature vs. sensor output voltage (typical case). temperature -40c 25c 105c 125c voltage (mv) 600 762 1012 adc 240 305 405 194 7734q?avr?02/12 at90pwm81/161 16. analog comparator the analog comparator compares the input valu es on the positive pin acmpx and negative pin acmpm or acmpmx. 16.1 features ? three analog comparators ? high speed anal og comparators ? 25mv or 10mv or 0 hysteresis ? four reference levels ? generation of configurable interrupts 16.2 overview the at90pwm81/161 features three fast analog comparators. each comparator has a dedicated input on the positive input, and the negative input of each comparator can be configured as: ? a steady value among the four internal reference levels defined by the v ref selected thanks to the refs1:0 bits in admux register ? a value generated from the internal dac ? an external analog input acmpmx when the voltage on the positive acmpn pin is higher than the voltage selected by the acnm multiplexer on the negative input, the analog comparator output, acno, is set. each comparator can trigger a separate interrupt, exclusive to the analog comparator. in addi- tion, the user can select interrupt triggering on comparator output rise, fall or toggle. the interrupt flags can also be used to synchronize adc or dac conversions. moreover, the comparator?s output of the comparator 1 can be set to trigger the timer/counter1 input capture function. a block diagram of the comparators and their surrounding logic is shown in figure 16-1 on page 195 . 195 7734q?avr?02/12 at90pwm81/161 figure 16-1. analog comparator block diagram. notes: 1. refer to figure 2-1 on page 3 and figure 2-2 on page 4 for analog comparator pin placement. 2. the voltage on v ref is defined in table 17-3, ?adc voltage reference selection.,? on page 218 . + - interrupt sensiti v ity control analog comparator 1 interrupt ac1ie t1 capture trigger ac1ice ac1if ac1o (to pscr) ac1is1 ac1is0 + - interrupt sensiti v ity control analog comparator 2 interrupt ac2ie ac2if ac2o (to psc2) ac2is1 ac2is0 acmp1 acmp2 ac2e n /3.20 /2.13 /1. 6 0 / 6 .40 acmpm3 ac1e n ac1m 2 1 0 ac2m 2 1 0 internal 2. 56 v re f erence refs1 refs0 + refs1 are f avcc + - interrupt sensiti v ity control analog comparator 3 interrupt ac3ie ac3if ac3is1 ac3is0 ac3e n ac3m 2 1 0 acmp3 acmpm2 acmpm1 acmp1 _ out acmpm vre f dac 10 dac result dace n acmp2 _ out acmp3 _ out ac1oe ac2oe ac3oe ac1h 2 1 0 ac2h 2 1 0 ac3h 2 1 0 ac3o (to psc2) acmp3 _ out _ a ac3oea ac2oi ac1oi ac3oi band gap band gap band gap refs0 vre f 196 7734q?avr?02/12 at90pwm81/161 figure 16-2. comparator psc links. 16.3 shared pins between an alog comparator and adc several analog comparators input pins can also be used as adc inputs, so it is possible to mea- sure the comparison voltages. however, when a comparator input is selected as the adc input, a spike occurs during the sampling phase of the adc. this may lead to an unwanted transition on the comparator output. so it is a safe software practice to devalidate the comparator output before measuring the voltage on one of the inputs. 16.4 analog comparator register description each analog comparator has its own control register. a dedicated register has been designed to consign the outputs and the flags of the three analog comparators. + - + - acmp1 acmp2 ac2e n acmpm3 ac1e n + - ac3e n acmp3 acmpm2 acmpm1 psc2 psci n 2a pscr psci n r psci n 2 psci n ra psci n rb 197 7734q?avr?02/12 at90pwm81/161 16.4.1 ac1con - analog comparator 1 control register ? bit 7? ac1en: analog comparator 1 enable bit set this bit to enable the analog comparator 1. clear this bit to disable the analog comparator 1. ? bit 6? ac1ie: analog comparator 1 interrupt enable bit set this bit to enable the analog comparator 1 interrupt. clear this bit to disable the analog comparator 1 interrupt. ? bit 5, 4? ac1is1, ac1is0: analog comparator 1 interrupt select bit these two bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 16-1 . ? bit 3? reserved ? bit 2, 1, 0? ac1m2, ac1m1, ac1m0: analog comparator 1 multiplexer register these three bits determine the input of the negative input of the analog comparator. the different settings are shown in table 16-2 . bit 7 6543210 ac1en ac1ie ac1is1 ac1is0 - ac1m2 ac1m1 ac1m0 ac1con read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 16-1. interrupt sensit ivity selection. ac1is1 ac1is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 16-2. analog comparator 1 negative input selection. ac1m2 ac1m1 ac1m0 description 000?v ref ?/6.40 001?v ref ?/3.20 010?v ref ?/2.13 011?v ref ?/1.60 100band gap voltage 101dac result 110analog comparator negative input (acmpm1 pin) 111analog comparator negative input (acmpm pin) 198 7734q?avr?02/12 at90pwm81/161 16.4.2 ac2con - analog comparator 2 control register ? bit 7? ac2en: analog comparator 2 enable bit set this bit to enable the analog comparator 2. clear this bit to disable the analog comparator 2. ? bit 6? ac2ie: analog comparator 2 interrupt enable bit set this bit to enable the analog comparator 2 interrupt. clear this bit to disable the analog comparator 2 interrupt. ? bit 5, 4? ac2is1, ac2is0: analog comparator 2 interrupt select bit these two bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 16-3 . ? bit 3? reserved ? bit 2, 1, 0? ac2m2, ac2m1, ac2m0: analog comparator 2 multiplexer register these three bits determine the input of the negative input of the analog comparator. the different setting are shown in table 16-4 . bit 7 6543210 ac2en ac2ie ac2is1 ac2is0 - ac2m2 ac2m1 ac2m0 ac2con read/write r/w r/w r/w r/w -r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 16-3. interrupt sensit ivity selection. ac2is1 ac2is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 16-4. analog comparator 2 negative input selection. ac2m2 ac2m1 ac2m0 description 000?v ref ?/6.40 001?v ref ?/3.20 010?v ref ?/2.13 011?v ref ?/1.60 100band gap voltage 101dac result 110analog comparator negative input (acmpm2 pin) 111analog comparator negative input (acmpm pin) 199 7734q?avr?02/12 at90pwm81/161 16.4.3 ac3con - analog comparator 3 control register ? bit 7? ac3en: analog comparator 3 enable bit set this bit to enable the analog comparator 3. clear this bit to disable the analog comparator 3. ? bit 6? ac3ie: analog comparator 3 interrupt enable bit set this bit to enable the analog comparator 3 interrupt. clear this bit to disable the analog comparator 3 interrupt. ? bit 5, 4? ac3is1, ac3is0: analog comparator 3 interrupt select bit these 2 bits determine the sensitivity of the interrupt trigger. the different setting are shown in table 16-5 . ? bit 3? ac3oea: analog comparator 3 alternate output enable set this bit to enable the analog comparator 3 alternate output pin. clear this bit to disable the analog comparator 3 alternate output pin. ? bit 2, 1, 0? ac3m2, ac3m1, ac3m0: analog comparator 3 multiplexer register these 3 bits determine the input of the negative input of the analog comparator. the different setting are shown in table 16-6 . bit 7 6543210 ac3en ac3ie ac3is1 ac3is0 ac3oea ac3m2 ac3m1 ac3m0 ac3con read/write r/w r/w r/w r/w - r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 16-5. interrupt sensit ivity selection. ac3is1 ac3is0 description 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on output falling edge 1 1 comparator interrupt on output rising edge table 16-6. analog comparator 2 negative input selection. ac3m2 ac3m1 ac3m0 description 000?v ref ?/6.40 001?v ref ?/3.20 010?v ref ?/2.13 011?v ref ?/1.60 100band gap voltage 101dac result 110analog comparator negative input (acmpm3 pin) 111analog comparator negative input (acmpm pin) 200 7734q?avr?02/12 at90pwm81/161 16.4.4 acnecon - analog comparator n extended control register ? bit 7..6? reserved ? bit 5? ac1oi: analog comparator n output invert set this bit to invert the analog comparator n output. clear this bit to keep the analog comparator n output. ? bit 4? ac1oe: analog comparator n output enable set this bit to enable the analog comparator n output pin. clear this bit to disable the analog comparator n output pin. ? bit 3 ? ac1ice: analog comparator 1 interrupt capture enable bit set this bit to enable the input capture of the timer/counter1 on the analog comparator event. the comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. in case ices1 bit ( ?tccr1b - timer/counter1 control register b? on page 97 ) is set high, the rising edge of ac3o is the capture/trigger event of the timer/counter1, in case ices1 is set to zero, it is the falling edge wh ich is taken into account. clear this bit to disable this function. in this case, no connection between the analog compara- tor and the input capture function exists. ? bit 2, 1, 0? acnh2, acnh1, acnh0: analog comparator n hysteresis select these 3 bits determine the hysteresis value of the analog comparator. the different setting are shown in table 16-7 . bit 7 6543210 acnoi acnoe ac1ice acnh2 acnh1 acnh0 acnecon read/write r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 16-7. analog ccomparator n hysteresis selection. ac1m2 ac1m1 ac1m0 description 000no hysteresis 001hysteresis + 10mv 010hysteresis - 10mv 011hysteresis 10mv 100reserved 101hysteresis + 25mv 110hysteresis - 25mv 111hysteresis 25mv 201 7734q?avr?02/12 at90pwm81/161 16.4.5 acsr - analog comparator status register ? bit 7? ac3if: analog comparator 3 interrupt flag bit this bit is set by hardware when comparator 3 output event triggers off the interrupt mode defined by ac3is1 and ac3is0 bits in ac3con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac3ie in ac3con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 6? ac2if: analog comparator 2 interrupt flag bit this bit is set by hardware when comparator 2 output event triggers off the interrupt mode defined by ac2is1 and ac2is0 bits in ac2con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac2ie in ac2con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 5? ac1if: analog comparator 1 interrupt flag bit this bit is set by hardware when comparator 1 output event triggers off the interrupt mode defined by ac1is1 and ac1is0 bits in ac1con register. this bit is cleared by hardware when the corresponding interrupt vector is executed in case the ac1ie in ac1con register is set. anyway, this bit is cleared by writing a logical one on it. this bit can also be used to synchronize adc or dac conversions. ? bit 4? reserved ? bit 3? ac3o: analog comparator 3 output bit ac2o bit is directly the output of the analog comparator 2. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 2? ac2o: analog comparator 2 output bit ac2o bit is directly the output of the analog comparator 2. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 1? ac1o: analog comparator 1 output bit ac1o bit is directly the output of the analog comparator 1. set when the output of the comparator is high. cleared when the output comparator is low. ? bit 0? reserved bit 7 6543210 ac3if ac2if ac1if - ac3o ac2o ac1o - acsr read/write r/w r/w r/w r/w - r r r initial value 0 0 0 0 0 0 0 0 202 7734q?avr?02/12 at90pwm81/161 16.4.6 didr0 - digital input disable register 0 ? bit 7:0 ? acmpmxd and acmpxd: acmpxmd, acmpxd & apm0+digital input disable when this bit is written logic one, the digital input buffer on the corresponding analog pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 16.4.7 didr1 - digital input disable register 1 ? bit 3, 0: acmpxmd, acmpxd & apm0+ digital input disable when this bit is written logic one, the digital in put buffer on the corresponding analog pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to one of these pins and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 adc8d acmp3d adc7d amp0-d adc5d acmp2d adc4d acmp3md adc3d acmpmd adc2d acmp2md adc1d adc0d acmp1d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 - - - -acmp1md amp0+d adc10d adc9d didr1 read/write - - r/w r/w r/w r/w r/w r/w initial value00000000 203 7734q?avr?02/12 at90pwm81/161 17. analog to digital converter - adc 17.1 features ? 10-bit resolution ? 0.5lsb integral non-linearity ? 2lsb absolute accuracy ? 8s - 250s conversion time ? up to 120ksps at maximum resolution ? 11 multiplexed single ended input channels ? one differential in put channels with accura te (5%) programmable gain 5, 10, 20, and 40 ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto triggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler ? temperature sensor the at90pwm81/161 features a 10-bit successive approximation adc. the adc is connected to an 15-channel analog multiplexer which al lows eleven single-ended input. the single-ended voltage inputs refer to 0v (gnd). the device also supports 2 differential voltage input combinations which are equipped with a programmable gain stage, providing amplification steps of 14db (5), 20db (10), 26db (20), or 32db (40) on the differential input voltage before the a/d conversion. on the amplified chan- nels, 8-bit resolution can be expected. the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 17-1 on page 204 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 210 on how to connect this pin. internal reference voltages of nominally 2.56v or av cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pi n by a capacitor for better noise performance. 204 7734q?avr?02/12 at90pwm81/161 figure 17-1. analog to digital converter block schematic. mux2 mux1 mux0 refs1 refs0 a d l a r adps2 adps1 adps0 adie aden adsc adate adif admux adcsra adts2 adts1 adts0 - adcsrb ed g e det ect or so u r c e s adc0 adc1 adc2 adc3 adc4 adc5 adc10 amp0+ - + amp0csr + - sa r 10 10 adch adcl co ar se/ fi n e dac 10 internal 2.56v re f e r e n c e avcc prescaler ck ck adc control ck adc adc conversion com plete i rq gnd ban d g ap adate adts3 temp sensor vcc/4 adc 8 adc9 amp0gs refs0,refs1 logic mux3 vref aref/adc6 amp0-/adc7 adssen adncdis adhsm 3 205 7734q?avr?02/12 at90pwm81/161 17.2 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1lsb. optionally, av cc or an internal 2.56v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by setting the adc enable bi t, aden in adcsra. voltage reference is set by the refs1 and refs0 bits in admux regist er, whatever the adc is enabled or not. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completed before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be tr iggered when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 17.3 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if th e trigger signal is still set when the conversion completes, a new conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. triggering from the psc?s synchronization signal is different as there is no flag. in this case, a new conversion is started at each triggering si gnal. however, a single shot mode can be acti- 206 7734q?avr?02/12 at90pwm81/161 vated by setting the bit adssen in adcsrb regist er. in this case the synchronization signal is blocked until the adch registed is read. figure 17-2. adc auto trigger logic. using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the adc interrupt flag, adif is cleared or not. the free running mode is not allowed on the amplified channels. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 17.4 prescaling and conversion timing figure 17-3. adc prescaler. by default, the successive approximation circ uitry requires an input clock frequency between 50khz and 2mhz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 2mhz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the prescaling is set by the adps bits in adcsra. adsc adif source 1 source n adts[2:0] co n versio n logic prescaler start clk adc . . . . edge detector adate 7 -bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/1 6 ck/32 ck/ 6 4 reset ade n start 207 7734q?avr?02/12 at90pwm81/161 the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. see ?changing channel or reference selection? on page 209 for details on differential conversion timing. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 3.5 adc clock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of an first conv ersion. when a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. for a summary of conversion times, see table 17-1 on page 209 . figure 17-4. adc timing diagram, first conv ersion (single conversion mode). sign and msb o f result lsb o f result adc clock adsc sample & hold adif adch adcl cycle n um b er ade n 1 212 13 14 1 5 1 6 1 7 18 1 9 20 21 22 23 24 2 5 1 2 first con v ersion n e x t con v ersion 3 mux and refs update mux and refs update con v ersion complete 208 7734q?avr?02/12 at90pwm81/161 figure 17-5. adc timing diagram, single conversion. figure 17-6. adc timing diagram, auto triggered conversion. figure 17-7. adc timing diagram, free running conversion. 4 5 6 7 8 9 10 11 12 13 14 1 5 1 6 sign and msb o f result lsb o f result adc clock adsc adif adch adcl cycle n um b er 12 one con v ersion n e x t con v ersion 3 sample & hold mux and refs update con v ersion complete mux and refs update 1 2 3 1 2 3 4 5 6 7 8 13 14 1 5 1 6 sign and msb o f result lsb o f result adc clock trigger source adif adch adcl cycle n um b er 12 one con v ersion n e x t con v ersion con v ersion complete prescaler reset adate prescaler reset sample & hold mux and refs update 14 1 5 1 6 sign and msb o f result lsb o f result adc clock adsc adif adch adcl cycle n um b er 12 one con v ersion n e x t con v ersion 34 con v ersion complete sample & hold mux and refs update 209 7734q?avr?02/12 at90pwm81/161 17.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 17.5.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection ? in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conversion has already started automatically, the next result will reflect the previous channel selection. su bsequent conversions will reflect the new channel selection table 17-1. adc conversion time. condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of conversion) 13.5 3.5 4 conversion time (cycles) 25 15.5 16 210 7734q?avr?02/12 at90pwm81/161 ? in free running mode, because the amplifier clear the adsc bit at the end of an amplified conversion, it is not possible to use the free running mode, unless adsc bit is set again by soft at the end of each conversion 17.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. if the external aref pin is connected to the adc, the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. the user may switch between av cc, aref pin and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 17.6 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure the adncdis bit is reset b. make sure the adate bit is reset c. make sure that the adc is enabled and is not busy converting (adsc reset). single conversion mode must be selected and the adc conversion complete interrupt must be enabled d. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted e. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed another possible procedure is possible for auto trigger conversions: a. make sure the adncdis bit is set b. make sure the adate bit is set c. enter adc noise reduction mode (or idle mode). the adc will start a conversion on the next triggering event d. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conversion complete interrupt 211 7734q?avr?02/12 at90pwm81/161 request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. if the adc is enabled in such sleep modes and the user wants to perform differential conver- sions, the user is advised to switch the adc off and on after waking up from sleep to prompt an extended conversion to get a valid result. 17.6.1 analog input circuitry the analog input circuitry for sing le ended channels is illustrated in figure 17-8 an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals with an output impedance of approximately 5kw or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, witch can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this mi nimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred kw or less is recommended. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 17-8. analog input circuitry. 17.6.2 analog noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: adcn i ih 1..100k c s/h = 14pf v cc /2 i il 212 7734q?avr?02/12 at90pwm81/161 a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digi- tal tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 17-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 17-9. adc power connections. 17.6.3 offset compensation schemes the gain stage has a built-in offset cancellation circ uitry that nulls the offset of differential mea- surements as much as possible. the remaining offset in the analog path can be measured directly by shortening both differential inputs using the ampxis bit with both inputs unconnected ( see ?amp0csr - amplifier 0 control and status register? on page 225 ). this offset residue can be then subtracted in software from the measurement results. using this kind of software based off- set correction, offset on any channel can be reduced below one lsb. 17.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5lsb). ideal value: 0lsb 100nf analog ground plane vcc avcc agnd aref gnd 10h 213 7734q?avr?02/12 at90pwm81/161 figure 17-10. offset error. ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5lsb below maximum). ideal value: 0lsb figure 17-11. gain error. ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0lsb output code v ref input voltage ideal adc actual adc o ff set error output code v ref input voltage ideal adc actual adc gain error 214 7734q?avr?02/12 at90pwm81/161 figure 17-12. integral non-linearity (inl). ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1lsb). ideal value: 0lsb figure 17-13. differential non- linearity (dnl). ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1lsb wide) will code to the same value. always 0.5lsb ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5lsb output code v ref input voltage ideal adc actual adc i n l output code 0 x 3ff 0 x 000 0 v ref input voltage d n l 1 lsb 215 7734q?avr?02/12 at90pwm81/161 17.7 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is: where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 17-3 on page 218 and table 17-4 on page 218 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, th e result is negative, and if this bit is zero, the result is posi- tive. figure 17-14 on page 216 shows the decoding of the differential input range. table 17-2 on page 217 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected wi th a reference voltage of v ref . adc v in 1023 ? v ref ------------------------- = adc v pos v neg ? () gain 512 ?? v ref ----------------------------------------------------------------------- = 216 7734q?avr?02/12 at90pwm81/161 figure 17-14. differential measurement range. 0 output code 0 x 1ff 0 x 000 v ref di ff erential input voltage (volts) 0 x 3ff 0 x 200 - v ref /gain /gain 217 7734q?avr?02/12 at90pwm81/161 example 1: ? admux = 0xed (adc3 - adc2, 10 gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300mv, voltage on adc2 is 500mv ? adcr = 512 10 (300 - 500) / 2560 = -400 = 0x270 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02 example 2: ? admux = 0xfb (adc3 - adc2, 1 gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300mv, voltage on adc2 is 500mv ? adcr = 512 1 (300 - 500) / 2560 = -41 = 0x029 ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29 17.8 adc register description the adc of the at90pwm81/161 is controlled through 3 different registers. the adcsra and the adcsrb registers which are the adc control and status registers, and the admux which allows to select the v ref source and the channel to be converted. the conversion result is stored on adch and adcl register which contain respectively the most significant bits and the less significant bits. 17.8.1 admux - adc multiplexer register table 17-2. correlation between input voltage and output codes. v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 bit 7 6543210 refs1 refs0 adlar - mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w -r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 218 7734q?avr?02/12 at90pwm81/161 ? bit 7, 6 ? refs1, 0: adc v ref selection bits these 2 bits determine the voltage reference for the adc and for the other analog devices. the different setting are shown in table 17-3 . if these bits are changed during a conversion, the change will not ta ke effect until this conversion is complete (it means while the adif bit in adcsra register is set). in case the internal v ref is selected, it is turned on as soon as an analog feature needed it is set. ? bit 5 ? adlar: adc left adjust result set this bit to left adjust the adc result. clear it to right adjust the adc result. the adlar bit affects the configuration of the adc result data registers. changing this bit affects the adc data registers immediately regardless of any on going conversion. for a com- plete description of this bit, see section ?adch and adcl - adc result data registers?, page 221 . ? bit 3, 2, 1, 0 ? mux3, mux2, mu x1, mux0: adc channel selection bits these 4 bits determine which analog inputs are connected to the adc input. the different set- ting are shown in table 17-4 . table 17-3. adc voltage reference selection. refs1 refs0 description voltage reference pe3/aref pin 0 0 external v ref external voltage reference 01av cc 1 0 internal 2.56v reference voltage external capacitor for decoupling of the internal reference voltage 1 1 internal 2.56v reference voltage pe3 pin free as port table 17-4. adc input channel selection. mux3 mux2 mux1 mux0 description 0000adc0 0001adc1 0010adc2 0011adc3 0100adc4 0101adc5 0110adc6 0111adc7 1000adc8 1001adc9 1010adc10 1011amp0 219 7734q?avr?02/12 at90pwm81/161 if these bits are changed during a conversion, the change will not ta ke effect until this conversion is complete (it means while the adif bit in adcsra register is set). 17.8.2 adcsra - adc control and status register a ? bit 7 ? aden: adc enable bit set this bit to enable the adc. clear this bit to disable the adc. clearing this bit while a conversion is running will take effe ct at the end of the conversion. ? bit 6? adsc: adc start conversion bit set this bit to start a conversion in single conver sion mode or to start the first conversion in free running mode. cleared by hardware when the conversion is complete. writing this bit to zero has no effect. the first conversion performs the initialization of the adc. ? bit 5 ? adate: adc auto trigger enable bit set this bit to enable the auto triggering mode of the adc. clear it to return in single conversion mode. in auto trigger mode the trigger source is selected by the adts bits in the adcsrb register. see table 17-6 on page 221 . ? bit 4? adif: adc interrupt flag set by hardware as soon as a conversion is complete and the data register are updated with the conversion result. cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif can be cleare d by writing it to logical one. ? bit 3? adie: adc interrupt enable bit set this bit to activate the adc end of conversion interrupt. clear it to disable the adc end of conversion interrupt. ? bit 2, 1, 0? adps2, adps1, ad ps0: adc prescaler selection bits these 3 bits determine the division factor between the system clock frequency and input clock of the adc. the different setting are shown in table 17-5 on page 220 . 1100temp sensor (vtemp) 1101v cc /4 1110band gap (vbg) 1111gnd table 17-4. adc input channel selection. (continued) mux3 mux2 mux1 mux0 description bit 7 6543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 220 7734q?avr?02/12 at90pwm81/161 17.8.3 adcsrb - adc control and status register b ? bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. set this bit if you wish to convert with an adc clock frequency higher than 200khz. ? bit 6 ? adncdis: adc noise canceller disable set this bit to disable automatic adc start when entering idle or adc noise reduction modes. clear it to enable automatic adc start when entering idle or adc reduction modes. the adncdis must be set before entering idle or adc noise reduction mo des if the adc is run- ning or auto triggered to prevent false adc restart. ? bit 5 ? reserved ? bit 4 ? adssen: adc single shot en able on psc?s syn chronization signals set this bit to enable single shot mode when auto trig ger on pscrasy & psc2asy. in this case a single conversion will be perform ed and pscrasy & psc2asy will be blocked until adch reading. clear it to enable continuo us conversion on pscrasy & psc2asy auto triggering. ? bit 3, 2, 1, 0? adts3:adts0: adc auto trigger source selection bits these bits are only necessary in case the adc works in auto trigger mode. it means if adate bit in adcsra register is set. in accordance with the table 17-6 on page 221 , these 3 bits select t he interrupt event which will generate the trigger of the start of conversion. the start of conversion will be generated by the rising edge of the selected interrupt flag whether the interrupt is enabled or not. table 17-5. adc prescaler selection. adps2 adps1 adps0 division factor 0002 0012 0104 0118 10016 10132 11064 111128 bit 7 6543210 adhsm adncdis - adssen adts3 adts2 adts1 adts0 adcsrb read/write r/w r/w - r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 221 7734q?avr?02/12 at90pwm81/161 in case of trig on pscnasy even t, there is no flag. so, if ad ssen is reset, a conversion will start each time the trig event appears an d the previous conversion is completed. 17.8.4 adch and adcl - adc re sult data registers when an adc conversion is complete, the conversion results are stored in these two result data registers. when the adcl register is read, the two adc result data registers can?t be updated until the adch register has also been read. consequently, in 10-bit configuration, the adcl register must be read first before the adch. nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the result thanks to the adlar bit in the adcsra register. like this, it is sufficient to only read adch to have the conversion result. 17.8.4.1 adlar = 0 table 17-6. adc auto trigger source selection. adts3 adts2 adts1 adts0 description 0000free running mode 0 0 0 1 analog comparator 1 0 0 1 0 external interrupt request 0 0 0 1 1 timer/counter1 overflow 0 1 0 0 timer/counter1 capture event 0 1 0 1 pscrasy event 0110psc2asy event 0 1 1 1 analog comparator 2 1 0 0 0 analog comparator 3 1001reserved 1010reserved 1011reserved 1100reserved 1101reserved 1110reserved 1111reserved bit 7 6543210 - - - - - - adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl read/write r r r r r r r r r rrrrrrr initial value 0 0 0 0 0 0 0 0 0 0000000 222 7734q?avr?02/12 at90pwm81/161 17.8.4.2 adlar = 1 17.8.5 didr0 - digital input disable register 0 ? bit 7:0 ? adc7d..adc0d: amp0-d and adc7:0 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 17.8.6 didr1 - digital input disable register 1 ? bit 2:0 ? amp0+d and adc10:8 digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to an analog pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 17.9 amplifier the at90pwm81/161 features one differential amplified channel with programmable 5, 10, 20, and 40 gain stage. despite the result is given by the 10bit adc, the amplifier has been sized to give a 8bits resolution. the negative input on the amplifier can be internally switched to the analog ground. however, amplifier characteristics are specified with differential inputs. because the amplifier is a switching capacitor amplifier, it needs to be clocked by a synchroniza- tion signal called in this document the amplifier sy nchronization clock. the amplifier samples the input value at the falling edge of the synchronization signal. this allow to measure analog sig- nals with same period as the synchronization. the maximum clock for the amplifier is 250khz. to ensure an accurate result in case of large voltage change, the amplifier input needs to have a quite stable sampled input value during at least four amplifier synchronization clock periods. bit 7 6543210 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 - - - - - - adcl read/write r r r r r r r r r rrrrrrr initial value 0 0 0 0 0 0 0 0 0 0000000 bit 76543210 adc8d acmp3d adc7d amp0-d adc5d acmp2d adc4d acmp3md adc3d acmpmd adc2d acmp2md adc1d adc0d acmp1d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 - - - - acmp1md amp0+d adc10d adc9d didr1 read/write - - r/w r/w r/w r/w r/w r/w initial value00000000 223 7734q?avr?02/12 at90pwm81/161 amplified conversions can be synchronized to psc events (see ?synchronization source description in one/two/four ramp modes.? on page 134 and ?synchronization source description in centered mode.? on page 135 ) or to the internal clock ck adc equal to eighth the adc clock frequency. in case the synchronization is done by the adc clock divided by eight, this synchro- nization is done automatically by the adc inte rface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (that is, all single conver- sions, and the first free r unning conversion) when ck adc2 is low will take the same amount of time as a single ended conversi on (13 adc clock cycles from the next prescaled clock cycle). a conversion initiated by the user when ck adc2 is high will take 14 adc clock cycles due to the synchronization mechanism. the normal way to use the amplifie r is to select a synchronization clock via the ampxts1:0 bits in the ampxcsr register. then the amplifier can be switched on, and the amplification is done on each synchronization event. the amplification is done independently of the adc. in order to start an amplified analog to digital conversion on the amplified channel, the admux must be configured as specified on table 17-4 on page 218 . the adc starting is done by setting the adsc (adc start conversion) bit in the adcsrb register. until the conversion is not achieved, it is not possible to start a conversion on another channel. on at90pwm81/161, conversion takes advantage of the amplifier characteristics to ensure minimum conversion time. as soon as a conversion is requested thanks to the adsc bit, the analog to digital conversion is started. in order to have a better understanding of the functioning of the amplifier synchroniza- tion, a timing diagram example is shown figure 17-15 on page 224 . in case the amplifier output is modified during the sample phase of the adc, the on-going con- version is aborted and restarted as soon as the output of the amplifier is stable as shown figure 17-16 on page 224 . the only precaution to take is to be sure that the trig signal (psc) frequency is lower than adcclk/4. it is also possible to auto trigger conversion on the amplified channel. in this case, the conver- sion is started at the next amplifier clock event following the last auto trigger event selected thanks to the adts bits in the adcsrb regist er. in auto trigger conversion, the free running mode is not possible unless the adsc bit in a dcsra is set by soft after each conversion. 224 7734q?avr?02/12 at90pwm81/161 figure 17-15. amplifier synchronization timing diagram with change on analog input signal. figure 17-16. amplifier synchronization timing diagram: behavior when adsc is set when the amplifier output is changing. valid sample delta v 4th sta b le sample signal to b e measured ampli _ clk (sync clock) ck adc ampli er sample ena b le ampli er hold value pscn _ as y psc block ampli er block adsc adc acti v ity adc adc sampling adc con v adc sampling adc con v adc result rea dy adc resu rea dy valid sample signal to b e measured ampli _ clk (sync clock) ck adc ampli er sample ena b le ampli er hold value pscn _ as y psc block ampli er block adsc adc acti v ity adc adc sampling adc con v adc sampling adc con v adc sampling a b orted adc result rea dy adc result rea dy 225 7734q?avr?02/12 at90pwm81/161 the block diagram of the two amplifiers is shown on figure 17-17 . figure 17-17. amplifiers block diagram. if apmp0gs bit is set, the amp0- input is open and pd5/amp0- pin is free for another use. at the same time the negative input of the amplifier is internally grounded. 17.10 amplifier c ontrol registers the configuration of the amplifier is controlled via the register amp0csr. then the start of con- version is done via the adc control and status registers. the conversion result is stored on adch and adcl register which contain respectively the most significant bits and the least significant bits. 17.10.1 amp0csr - amplifier 0 control and status register ? bit 7 ? amp0en: amplifier 0 enable bit set this bit to enable the amplifier 0. clear this bit to disable the amplifier 0. clearing this bit while a conversion is running will take effe ct at the end of the conversion. ? bit 6? amp0is: amplifier 0 input shunt set this bit to short-circuit the amplifier 0 input. if amp0gs is set, the ground switch is released during shunt of inputs. clear this bit to norma lly use the amplifier 0. amp0ts1 amp0ts0 amp0en amp0is amp0g1 amp0g0 amp0csr + - sa m pli n g amp0+ amp0- to w a r d a d c m u x (amp0) sam p l i n g cl o ck adck/ 8 01 10 00 - 1 1 psc2asy pscrasy amp0gs no short amp0+ gnd bit 7 6543210 amp0en amp0is amp0g1 amp0g0 amp0gs - amp0ts1 amp0ts0 amp0csr read/write r/w r/w r/w r/w - - r/w r/w initial value 0 0 0 0 0 0 0 0 226 7734q?avr?02/12 at90pwm81/161 ? bit 5, 4? amp0g1, 0: amplifier 0 gain selection bits these two bits determine the gain of the amplifier 0. the different setting are shown in table 17-7 . to ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite stable input value during at least four amplifier synchronization clock periods. ? bit 3? amp0gs: amplifier 0 ground select of amp0 this bit select negative input of the amplifier: set this bit to ground the amplifier 0 negative input. clear this bit to normally use the amplifier 0 differential input. ? bit 1, 0? amp0ts1, amp0ts0: amplifier 0 trigger source selection bits in accordance with the table 17-8 , these two bits select the even t which will generate the trigger for the amplifier 0. this trigger source is necessary to start the conversion on the amplified channel. table 17-7. amplifier 0 gain selection. amp0g1 amp0g0 description 00gain 5 01gain 10 10gain 20 11gain 40 table 17-8. amp0 auto trigger source selection. amp0ts1 amp0ts0 description 0 0 auto synchronization on adc clock/8 0 1 trig on pscrasy 10 1 1 trig on psc2asy 227 7734q?avr?02/12 at90pwm81/161 18. digital to analog converter - dac 18.1 features ? 10 bits resolution ? 8 bits linearity ? 0.5lsb accuracy between 100mv and av cc - 100mv ? v out = dac v ref /1023 ? the dac could be connected to the negative inputs of the analog comparators the at90pwm81/161 features a 10-bit digital to analog converter. this dac can be used for the analog comparators. the dac has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 210 on how to connect this pin. the reference voltage is the same as the one used for the adc. see ?admux - adc multiplexer register? on page 217. these nominally 2.56v v ref or av cc are provided on-chip. the voltage reference may be externally decoupled at the a ref pin by a capacitor for better noise performance. figure 18-1. digital to analog converter block schematic. dac dala dae n - daate dats2 dats1 dats0 10 dach dacl daco n 10 10 10 vre f dac result update d ac trigger dac lo w b its dac high b its edge detector sources 228 7734q?avr?02/12 at90pwm81/161 18.2 operation the digital to analog converter generates an analog signal proportional to the value of the dac registers value. in order to have an accurate sampling frequency control, there is the possibility to update the dac input values through different trigger events. 18.3 starting a conversion the dac is configured thanks to the dacon register. as soon as the daen bit in dacon reg- ister is set, the dac converts the value present on the dach and dacl registers in accordance with the register dacon setting. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the dac auto trigger enable bi t, daate in dacon. the trigger source is selected by setting the dac trigger select bits, dats in dacon (see description of the dats bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the dac converts the value present on the da ch and dacl registers in accordance with the register dacon setting. this provides a method of starting conversions at fixed intervals. if the trigger signal is still set when the conversion co mpletes, a new conversion will not be started. if another positive edge occurs on the trigger signal during conv ersion, the edge will be ignored. note that an interr upt flag will be set even if the specific in terrupt is disabled or the gl obal inter- rupt enable bit in sreg is cleared. a conver sion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 18.3.1 dac voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the dac. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the dac through a passive switch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. when the external aref pin is connected to the dac, the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedance voltmeter. note that v ref is a high impedance source, and only a capacitive load should be connected in a system. the user may switch between av cc, av cc and 2.56v as reference selection. the first dac con- version result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 18.4 dac register description the dac is controlled via three dedicated registers: ? the dacon register which is used for dac configuration ? dach and dacl which are used to set the value to be converted 18.4.1 dacon - digital to analog conversion control register bit 7 6543210 daate dats2 dats1 dats0 - dala - daen dacon read/write r/w r/w r/w r/w - r/w - r/w initial value 0 0 0 0 0 0 0 0 229 7734q?avr?02/12 at90pwm81/161 ? bit 7 ? daate: dac auto trigger enable bit (not useful, may be left for compatibility) set this bit to update the dac input value on the positive edge of the trigger signal selected with the dacts2-0 bit in dacon register. clear it to automatically update the dac inpu t when a value is wri tten on dach register. ? bit 6:4 ? dats2, dats1, dats0: dac trigger selection bits (not useful, may be left for compatibility) these bits are only necessary in case the dac works in auto trigger mode. it means if daate bit is set. in accordance with the table 18-1 , these 3 bits select the inte rrupt event which will generate the update of the dac input values. the up date will be genera ted by the rising e dge of the selected interrupt flag whether the interrupt is enabled or not. ? bit 2 ? dala: digital to analog left adjust set this bit to left adjust the dac input data. clear it to right adjust the dac input data. the dala bit affects the configuration of the dac data registers. changing this bit affects the dac output on the next dach writing. ? bit 1 ? reserved ? bit 0 ? daen: digital to analog enable bit set this bit to enable the dac. clear it to disable the dac. 18.4.2 dach and dacl - digital to analog converter input register dach and dacl registers contain the value to be converted into analog voltage. writing the dacl register forbid the update of the input value until dach has not been written too. so the normal way to write a 10-bit value in the dac register is firstly to write dacl the dach. in order to work easily with only 8 bits, there is the possibility to left adjust the input value. like this it is sufficient to writ e dach to update the dac value. table 18-1. dac auto trigger source selection. dats2 dats1 dats0 description 0 0 0 analog comparator 0 0 0 1 analog comparator 1 0 1 0 external interrupt request 0 011reserved 100reserved 101reserved 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event 230 7734q?avr?02/12 at90pwm81/161 18.4.2.1 dala = 0 18.4.2.2 dala = 1 to work with the 10-bit dac, two registers have to be updated. in order to avoid intermediate value, the dac input values which are really converted into analog signal are buffering into unreachable registers. in normal mode, the update of the shadow register is done when the reg- ister dach is written. in case daate bit is set, the dac input va lues will be updated on the trigger event selected through dats bits. in order to avoid wrong dac input values, the update can only be done after having written respectively dacl and dach registers. it is possi ble to work on 8-bit configuration by only writ- ing the dach value. in this case, update is done each trigger event. in case daate bit is cleared, the dac is in an automatic update mode. writing the dach regis- ter automatically update the dac input values with the dach and dacl register values. it means that whatever is the configuration of the daate bit, changing the dacl register has no effect on the dac output until the dach register has also been updated. so, to work with 10 bits, dacl must be written first before dach. to work with 8-bit conf iguration, writing dach allows the update of the dac. bit 7 6543210 - - - - - - dac9 dac8 dach dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 dacl read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0000000 bit 7 6543210 dac9 dac8 dac7 dac6 dac5 dac4 dac3 dac2 dach dac1 dac0 - - - - - - dacl read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0000000 231 7734q?avr?02/12 at90pwm81/161 19. debugwire on-chip debug system 19.1 features ? complete program flow control ? emulates all on-chip functions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of program break po ints (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 19.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 19.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. figure 19-1. the debugwire setup. figure 19-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. when designing a system where debugwire will be used, the following observations must be made for correct operation: dw g n d dw(reset) vcc 1.8v - 5 . 5 v 232 7734q?avr?02/12 at90pwm81/161 ? pull-up resistors on the dw/(reset) line must not be smaller than 10kw. the pull-up resistor is not required for debugwire functionality ? connecting the reset pin directly to v cc will not work ? capacitors connected to th e reset pin must be disconne cted when using debugwire ? all external reset sources must be disconnected 19.4 software break points the debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instructi on in the program memory. the instruction replaced by the break instruction will be stored. when program execution is contin- ued, the stored instruction will be executed before continuing from the program memory. a break can be inserted manu ally by putting the break in struction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio th rough the debugwire inte rface. the use of brea k points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 19.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/o functions when running at full speed, that is, when the program in the cpu is running. when the cpu is stopped, care must be taken while accessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 19.6 debugwire re lated register in i/o memory the following section describes the registers used with the debugwire. 19.6.1 dwdr - debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 dwdr[7:0] dwdr read/writer/wr/wr/wr/wr/wr/wr/wr/w initial value00000000 233 7734q?avr?02/12 at90pwm81/161 20. boot loader support ? read -while-write self-programming in at90pwm81/161, the boot loader support prov ides a real read-while-write self-program- ming mechanism for downloading and uploading pr ogram code by the mcu itself. this feature allows flexible application software updates c ontrolled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. the pr ogram code within the boot lo ader section has the capability to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configured with fuses and the boot loader has two separate sets of boot lock bits which ca n be set independently. this give s the user a unique flexibility to select different levels of protection. 20.1 boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 21-12 on page 254 ) used during programming. the page organiz ation does not affect normal operation. 20.2 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 20-2 on page 236 ). the size of the different sections is configured by the bootsz fuses as shown in table 20-7 on page 246 and figure 20-2 on page 236 . these two sections can have different level of protecti on since they have different sets of lock bits. 20.2.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 20-2 on page 237 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 20.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 20-3 on page 237 . 20.3 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two 234 7734q?avr?02/12 at90pwm81/161 sections that are configured by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-whi le-write (rww) section and the no read-while- write (nrww) section. the limit between the rww- and nrww sections is given in table 20- 9 on page 247 and figure 20-2 on page 236 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation note that the user software can never read any code that is located inside the rww section dur- ing a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 20.3.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (that is, by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory cont rol and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is com- pleted, the rwwsb must be cleared by software before reading code located in the rww section. see ?spmcsr - store program memory control and status register? on page 238 for details on how to clear rwwsb. 20.3.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 20-1. read-while-write features. which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 235 7734q?avr?02/12 at90pwm81/161 figure 20-1. read-while-write vs. no read-while-write. read-while-write (rww) section n o read-while-write ( n rww) section z -pointer addresses rww section z -pointer addresses n rww section cpu is halted during the operation code located in n rww section can b e read during the operation 236 7734q?avr?02/12 at90pwm81/161 figure 20-2. memory sections. note: 1. the parameters in the figure above are given in table 20-7 on page 246 . 20.4 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu ? to protect only the boot loader flash section from a software update by the mcu ? to protect only the application flash section from a software update by the mcu ? allow software update in the entire flash see table 20-2 on page 237 and table 20-3 on page 237 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the pro- gramming of the flash memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. 0 x 0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0 x 0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0 x 0000 flashend application flash section flashend end rww start n rww application flash section boot loader flash section boot loader flash section end rww start n rww end rww start n rww 0 x 0000 end rww , end application start n rww , start boot loader application flash section application flash section application flash section read-while-write section n o read-while-write section read-while-write section n o read-while-write section read-while-write section n o read-while-write section read-while-write section n o read-while-write section end application start boot loader end application start boot loader end application start boot loader 237 7734q?avr?02/12 at90pwm81/161 note: 1. ?1? means unprogrammed, ?0? means programmed. note: 1. ?1? means unprogrammed, ?0? means programmed. 20.5 entering the b oot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command rece ived via spi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and th e fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed. table 20-2. boot lock bit0 protection modes (application section) (1) . blb0 mode blb02 blb01 protection 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 30 0 spm is not allowed to write to the a pplication section, and lpm executing from the boot loader sect ion is not allowed to read from the application section. if interrupt vectors are pl aced in the boot loader section, interrupts are disabled while exec uting from the application section. 40 1 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt ve ctors are placed in the boot loader section, interrupts are disabled wh ile executing from the application section. table 20-3. boot lock bit1 protection modes (boot loader section) (1) . blb1 mode blb12 blb11 protection 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 30 0 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 40 1 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled whil e executing from the boot loader section. table 20-4. boot reset fuse (1) . bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 20-7 on page 246 ) 238 7734q?avr?02/12 at90pwm81/161 20.5.1 spmcsr - store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready in terrupt will be ex ecuted as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one ) by hardware. when the rwws b bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alter natively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within three clock cycles will read a byte from the signat ure row into the dest ination register. see ?reading the signature row from software? on page 243 for details. an spm instruction within four cycles after sigrd and spmen are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww section, the user software must wait unt il the programming is complet ed (spmen will be cl eared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww secti on. the rww section cannot be re-enabled while the flash is busy with a page erase or a page wr ite (spmen is set). if the rwwsre bit is writ- ten while the flash is being loaded, the flas h load operation will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in r0. the data in r1 and the address in the z-pointe r are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles after blbset and spmen are set in the spmcsr reg- ister, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 242 for details. bit 7 6 5 4 3 2 1 0 spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 239 7734q?avr?02/12 at90pwm81/161 ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon co mpletion of a page write, or if no spm instruction is ex ecuted within four clock cycles. the cpu is halted during the ent ire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: self programming enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt or pgers, the following spm instruction will have a spe- cial meaning, see description abo ve. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 20.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 21-12 on page 254 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 20-3 on page 240 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. bit 1514131211109 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 240 7734q?avr?02/12 at90pwm81/161 figure 20-3. addressing the flash during spm (1) . note: 1. the different variables used in figure 20-3 are listed in table 20-10 on page 247 . 20.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase: ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase: ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 245 for an assembly code example. program memor y 0 1 1 5 z - register bit 0 z pagemsb word address withi n a page page address withi n the flash z pcmsb i n structio n word pag e pcword[pagemsb:0]: 00 01 02 pagee n d pag e pcword pcpage pcmsb pagemsb program cou n ter 241 7734q?avr?02/12 at90pwm81/161 20.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section:the nrww section can be read during the page erase ? page erase to the nrww section:the cpu is halted during the operation 20.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 20.7.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page write to the rww section:the nrww section can be read during the page write ? page write to the nrww section:the cpu is halted during the operation 20.7.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant in terrupt when the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in section ?moving interrupts between application and boot space?, page 65 . 20.7.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 20.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in section ?moving interrupts between application and boot space?, page 65 , or the interrupts must be disabled. before addressing the rww section after the programming is 242 7734q?avr?02/12 at90pwm81/161 completed, the user software must clea r the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 245 for an example. 20.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that may prevent the a pplication and boot loader section from any soft- ware update by the mcu. see table 20-2 on page 237 and table 20-3 on page 237 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t ca re during this operation, but for fu ture compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when pro- gramming the lock bits the entire flash can be read during the operation. 20.7.8 eeprom write prevents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 20.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruc- tion is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits will auto-clear upon completion of reading the lo ck bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blb- set and spmen are cleared, lpm will work as described in the instruction set manual . the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 21-4 on page 249 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after the blbset and spmen bits are set in the spmcsr, bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 7654 3210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 243 7734q?avr?02/12 at90pwm81/161 the value of the fuse high byte (fhb) will be load ed in the destination re gister as shown below. refer to table 21-5 on page 250 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbs et and spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loaded in the desti nation register as shown below. refer to table 21-4 on page 249 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 20.7.10 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 20-5 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after t he sigrd and spmen bits are set in spmcsr, the signature byte value will be loaded in the desti nation register. the sigrd and spmen bits will auto-clear upon completion of reading the signature row lock bits or if no lpm instruction is executed within three cpu cycles. when s igrd and spmen are cleared, lpm will work as described in the ?avr instruction set? description. bit 7654 3210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 7654 3210 rd ???? efb3efb2efb1efb0 table 20-5. signature row addressing. signature byte address at90pwm81 data at90pwm161 data device id 0, manufacturer id 0x00 1eh 1eh oscal 8m, rc-osc calibration 0x01 xxh xxh device id 1, flash size 0x02 93h 94h reserved 0x03 xxh xxh device id 2, device 0x04 88h 8bh temperature sensor offset : tsoffset 0x05 xxh xxh reserved 0x06 xxh xxh temperature sensor gain : tsgain (1) 0x07 xxh xxh lot number at sort, byte 2, ascii 0x0e xxh xxh lot number at sort, byte 1, ascii (most left lot#) 0x0f xxh xxh lot number at sort, byte 2, ascii 0x10 xxh xxh lot number at sort, byte 1, ascii 0x11 xxh xxh lot number at sort, byte 2, ascii 0x12 xxh xxh lot number at sort, byte 1, ascii 0x13 xxh xxh final test amb v ref : low byte (2) 0x3c xxh xxh 244 7734q?avr?02/12 at90pwm81/161 note: 1. tsgain typical value is 0x80=128 2. see note 3 3. final test amb v ref high byte and low byte: typical values are for v ref = 2.56v: high byte = 0x0a low byte = 0x00 this means: final test amb v ref = 0x0a00 = 2560 = v ref 1000 4. see note 3 which details the value format 5. see note 3 which details the value format 20.7.11 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient po wer supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 20.7.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 20-6 shows the typical pro- gramming time for flash accesses from the cpu. final test amb v ref : high byte (3) 0x3d xxh xxh final test hot v ref : low byte (only a read) (4) 0x3e xxh xxh final test hot v ref : high byte (only a read) (5) 0x3f xxh xxh table 20-5. signature row addressing. (continued) signature byte address at90pwm81 data at90pwm161 data table 20-6. spm programming time. symbol min. programming time max. programming time flash write (page erase, page write, and write lock bits by spm) 3.7ms 4.5ms 245 7734q?avr?02/12 at90pwm81/161 20.7.13 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 248 7734q?avr?02/12 at90pwm81/161 21. memory programming 21.1 program and data memory lock bits the at90pwm81/161 provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 21-2 . the lock bits can only be erased to ?1? with the chip erase command. notes: 1. ?1? means unprogrammed, ?0? means programmed. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed. table 21-1. lock bit byte (1) lock bit byte bit no. desc ription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 21-2. lock bit protection modes (1)(2) . memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled 21 0 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode (1) 30 0 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode (1) 249 7734q?avr?02/12 at90pwm81/161 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed. 21.2 fuse bits the at90pwm81/161 has three fuse bytes. table 21-4 to table 21-6 on page 251 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. see table 7-2 on page 53 for bodlevel fuse decoding. 21.2.1 psc output behavior during reset for external component safety reason, the state of psc outputs during reset can be pro- grammed by fuses pscrv, pscrrb & psc2rb. these fuses are located in the extended fuse byte (see table 21-4 ). table 21-3. lock bit protection modes (1)(2) . only atmega88/168. blb0 mode blb02 blb01 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application se ction, and lpm executing from the boot loader section is not allowed to read from the applicati on section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled wh ile executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from t he boot loader section. if interrupt vectors are placed in the application section, interrup ts are disabled while executing from the boot loader section. table 21-4. extended low fuse byte. extended fuse byte bit no description default value psc2rb 7 psc2 reset behavior 1 psc2rba 6 psc2 reset behavior for out22 & 23 1 pscrrb 5 psc reduced reset behavior 1 pscrv 4 pscout & pscoutr reset value 1 pscinrb 3 psc & pscr inputs reset behavior 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 0 (programmed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) 250 7734q?avr?02/12 at90pwm81/161 pscrv gives the state low or high which will be forced on psc outputs selected by psc0rb & psc2rb fuses. if pscrv fuse equals 0 (programmed), the selected psc outputs will be forced to low state. if pscrv fuse equals 1 (u nprogrammed), the selected psc output s will be forced to high state. if pscrrb fuse equals 1 (unprogrammed), pscoutr0 & pscoutr1 keep a standard port behavior. if psc0rb fuse equals 0 (programmed), pscoutr0 & pscoutr1 are forced at reset to low level or high level according to pscrv fuse bit. in this second case, pscoutr0 & pscoutr1 keep the forced state until psoc0 register is written. if psc2rb fuse equals 1 (unprogrammed), pscout20 & pscout21 keep a standard port behavior. if psc2rb fuse equals 0 (programmed), pscout20 & pscout21 are forced at reset to low level or high leve l according to pscrv fuse bit. in this second case, pscout20 & pscout21 keep the forced state until psoc2 register is written. if psc2rba fuse equals 1 (unprogrammed), pscout22 & pscout23 keep a standard port behavior. if psc2rba fuse equals 0 (programmed), pscout22 & pscout23 are forced at reset to low level or high leve l according to pscrv fuse bit. in this second case, pscout22 & pscout23 keep the forced state until psoc2 register is written. 21.2.2 psc input behavior during reset for power consumption under reset reason, the state of psc & pscr inputs during reset can be programmed by fuse pscinrb. if pscinrb fuse equals 1 (unprogrammed), psc & pscr input keep a standard port behavior. if pscinrb fuse equals 0 (programmed), psc & pscr input pull-up are forced while the reset is active. affected pins are pscin2, pscinr, pscin2a, pscinra. to prevent any conflict on pd1, this fuse has no effect on pscinrb. notes: 1. see ?alternate functions of port e? on page 80 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?watchdog timer configuration.? on page 60 for details. 4. the default value of bootsz1..0 results in maximum boot size. see table 21-8 on page 252 for details. table 21-5. fuse high byte. high fuse byte bit no. desc ription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bootsz1 2 select boot size (see table 20-7 on page 246 for details) 0 (programmed) (4) bootsz0 1 select boot size (see table 20-7 on page 246 for details) 0 (programmed) (4) bootrst 0 select reset vector 1 (unprogrammed) 251 7734q?avr?02/12 at90pwm81/161 note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 5-4 on page 30 for details. 2. the default setting of cksel3..0 result s in internal rc oscillator @ 8mhz. see table 5-1 on page 28 for details. 3. the ckout fuse allows the system clock to be output on portd0. see ?clock output buf- fer? on page 34 for details. 4. see ?system clock prescaler? on page 39 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 21.2.3 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 21.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space, the signature row. 21.3.1 signature bytes table 21-7. device id bytes for at90pwm81/161 devices. for the at90pwm81/161 the signature bytes are: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x002: 0x93 (indicates 8kb flash memory). 3. 0x004: 0x88 (indicates the at90pw m81 device when 0x002 is 0x93). 0x004: 0x8b (indicates the at90pw m161 device when 0x002 is 0x94). table 21-6. fuse low byte. low fuse byte bit no. description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) device device id bytes 0x004 0x002 0x000 at 9 0 p w m 8 1 8 8 9 3 1 e at90pwm161 8b 94 1e 252 7734q?avr?02/12 at90pwm81/161 21.4 calibration byte the at90pwm81/161 has a byte calibration val ue for the internal rc oscillator. this byte resides in the byte of address 0x003 in the signat ure address space. during reset, this byte is automatically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. 21.5 parallel programming paramete rs, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90pwm81/161. pulses are assumed to be at least 250ns unless otherwise stated. 21.5.1 signal names in this section, some pins of the at90pwm 81/161 are referenced by signal names describing their functionality during parallel programming, see figure 21-1 and table 21-8 . pins not described in table 21-8 are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 21-10 on page 253 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 21-11 on page 253 . figure 21-1. parallel programming. table 21-8. pin name mapping. signal name in programming mode pin name i/o function rdy/bsy aref o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd1 i write pulse (active low) xa0 pd5 i xtal action bit 0 vcc gnd xtal1/pe1 xa0 rdy/bsy oe reset/pe0 +5v avcc +5v aref +12v pe 2 pd6 pd5 pd1 pd2 wr xa1/bs2 pagel/bs1 data pb[7:0] 253 7734q?avr?02/12 at90pwm81/161 xa1/bs2 pd6 i xtal action bit 1 byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) pagel/bs1 pe2 i program memory and eeprom data page load byte select 1 (?0? selects low byte, ?1? selects high byte) data pb[7:0] i/o bi-directional data bus (output when oe is low) table 21-9. pin values used to enter programming mode. pin symbol value xa1/bs2 prog_enable[3] 0 xa0 prog_enable[2] 0 oe prog_enable[1] 0 wr prog_enable[0] 0 table 21-10. xa1 and xa0 coding. xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1) 0 1 load data (high or low data byte for flash determined by bs1) 1 0 load command 1 1 no action, idle table 21-11. command byte bit coding. command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 21-8. pin name mapping. (continued) signal name in programming mode pin name i/o function 254 7734q?avr?02/12 at90pwm81/161 21.6 serial programming pin mapping 21.7 parallel programming 21.7.1 enter programming mode the following algorithm puts the device in parallel (high-voltage) > programming mode: 1. set prog_enable pins listed in table 21-9 on page 253 to ?0000?, reset pin to ?0? and v cc to 0v. 2. apply 4.5v - 5.5v between v cc and gnd. ensure that v cc reaches at least 1.8v within the next 20s. 3. wait 20s - 60s, and apply 11.5v - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. 5. wait at least 300s before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. if the rise time of the v cc is unable to fulfill the requiremen ts listed above, th e following alterna- tive algorithm can be used. 1. set prog_enable pins listed in table 21-9 on page 253 to ?0000?, reset pin to ?0? and v cc to 0v. 2. apply 4.5v - 5.5v between v cc and gnd. 3. monitor v cc , and as soon as v cc reaches 0.9v - 1.1v, apply 11.5v - 12.5v to reset. 4. keep the prog_enable pins unchanged for at least 10s after the high-voltage has been applied to ensure the prog_enable signature has been latched. table 21-12. no. of words in a page and no. of pages in the flash. device flash size page size pcword no. of pages pcpage pcmsb at 9 0 p w m 8 1 4k words (8kbytes) 32 words pc[4:0] 128 pc[11:5] 11 at90pwm161 8k words (16kbytes) 64 words pc[5:0] 128 pc[12:6] 12 table 21-13. no. of words in a page and no. of pages in the eeprom. device eeprom size page size pcword no. of pages pcpage eeamsb at90pwm81/161 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 table 21-14. pin mapping serial programming. symbol pins i/o description mosi i serial data in miso o serial data out sck i serial clock 255 7734q?avr?02/12 at90pwm81/161 5. wait until v cc actually reaches 4.5v -5.5v before giving any parallel programming commands. 6. exit programming mode by power the device down or by bringing reset pin to 0v. 21.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading 21.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during ch ip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 21.7.4 programming the flash the flash is organized in pages, see table 21-12 on page 254 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 256 7734q?avr?02/12 at90pwm81/161 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes (see figure 21-3 on page 257 for signal waveforms). f. repeat b through e until the entire buffer is filled or until all data within the page is loaded while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash . this is illustrated in figure 21-2 on page 257 . note that if less than eight bits are required to address words in the page (pagesize <256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 21-3 on page 257 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. 257 7734q?avr?02/12 at90pwm81/161 figure 21-2. addressing the flash, which is organized in pages (1) . note: 1. pcpage and pcword are listed in table 21-12 on page 254 . figure 21-3. programming the flash waveforms (1) . note: 1. ?xx? is don?t care. the letters refer to the programming description above. 21.7.5 programming the eeprom the eeprom is organized in pages, see table 21-13 on page 254 . when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 255 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled program memor y word address withi n a page page address withi n the flash i n structio n word pag e pcword[pagemsb:0]: 00 01 02 pagee n d pag e pcword pcpage pcmsb pagemsb program cou n ter rd y /bs y wr oe reset + 12v 0 x 10 addr. low addr. high data data l ow data high addr. low data l ow data high xa1/bs2 xa0 pagel/bs1 xtal1 xx xx xx abcdeb cdegh f 258 7734q?avr?02/12 at90pwm81/161 l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 21-4 for signal waveforms). figure 21-4. programming the eeprom waveforms. 21.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 255 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 21.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 255 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 21.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 255 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. rd y /bs y wr oe reset + 12v 0 x 11 addr. high data addr. l ow data addr. low data xx xa1/bs2 xa0 pagel/bs1 xtal1 xx agbceb c el k 259 7734q?avr?02/12 at90pwm81/161 21.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 255 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 21.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 255 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. figure 21-5. programming the fuses waveforms. 21.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 255 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. rdy/bsy wr oe reset +12v 0x40 data data xx xa1/bs2 xa0 pagel/bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte 260 7734q?avr?02/12 at90pwm81/161 21.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 255 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. figure 21-6. mapping between bs1, bs2 and the fuse and lock bits during read. 21.7.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 255 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 21.7.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 255 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 e x tended fuse byte 261 7734q?avr?02/12 at90pwm81/161 21.8 serial downloading both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 21-14 on page 254 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. figure 21-7. serial programming and verify (1) . notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 1.8v - 5.5v. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz 21.8.1 serial programming algorithm when writing serial data to the at90pwm81/161, data is clocked on the rising edge of sck. when reading data from the at90pwm81/161, data is clocked on the falling edge of sck. see figure 21-8 on page 263 for timing details. to program and verify the at90pwm81/161 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 21-16 on page 263 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this vcc gnd xtal1 sck_a miso_a mosi_a reset +1.8v - 5.5v avcc +1.8v - 5.5v (2) 262 7734q?avr?02/12 at90pwm81/161 case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will no t work if the communic ation is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 8 msb of the address. if polling is not used, the user must wait at least t wd_flash before issuing the next page. (see table 21-15 on page 263 .) accessing the serial programming inter- face before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if pollin g is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 21-15 on page 263 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 21.8.2 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at th e time the device is ready for a new page, the programmed value will read correctly. this is used to determine w hen the next page can be writ- ten. note that the entire page is written simultaneously and any address within the page can be used for polling. data po lling of the flash will not work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. see table 21-15 on page 263 for t wd_flash value. 21.8.3 data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being programmed will give the value 0xff. at the time the device is ready for a new byte, the programmed value will read corr ectly. this is used to determine when the next byte can be written. this will not work for the value 0xff, but th e user should have the following in mind: as a chip-erased device contains 0xff in all locations, progra mming of addresses that are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re-pro- grammed without chip eras ing the device. in this case, data po lling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 21-15 on page 263 for t wd_eeprom value. 263 7734q?avr?02/12 at90pwm81/161 figure 21-8. serial programming waveforms. table 21-15. minimum wait delay before writing the next flash or eeprom location. symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 3.6ms t wd_erase 9.0ms msb msb lsb lsb serial clock i n put (sck) serial data i n put (mosi) (miso) sample serial data output table 21-16. serial programming instruction set. instruction instruction format operation byte 1 byte 2 byte 3 byte 4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low chip erase 1010 1100 100x xxxx xxxx xx xx xxxx xxxx chip erase eeprom and flash read program memory 0010 h 000 000 a aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b load program memory page 0100 h 000 000x xxxx xx bb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address write program memory page 0100 1100 000 a aaaa bb xx xxxx xxxx xxxx write program memory page at address a : b read eeprom memory 1010 0000 000x xx aa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b write eeprom memory 1100 0000 000x xx aa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page write eeprom memory page (page access) 1100 0010 00xx xx aa bbbb bb00 xxxx xxxx write eeprom page at address a : b read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 21-1 on page 248 for details 264 7734q?avr?02/12 at90pwm81/161 note: a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care. 21.8.4 spi serial programming characteristics for characteristics of the spi module see ?spi serial programming characteristics? on page 264 . write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 21-1 on page 248 for details read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b write fuse bits 1010 1100 10 10 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 21-6 on page 251 for details write fuse high bits 1010 1100 10 10 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 21-5 on page 250 for details write extended fuse bits 1010 1100 10 10 0100 xxxx xxxx xxxx xxii set bits = ?0? to program, ?1? to unprogram. see table 21-4 on page 249 for details read fuse bits 0101 0000 00 00 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table 21-6 on page 251 for details read fuse high bits 0101 1000 00 00 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 21-5 on page 250 for details read extended fuse bits 0101 0000 00 00 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 21-4 on page 249 for details read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command table 21-16. serial programming instruction set. (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte 4 265 7734q?avr?02/12 at90pwm81/161 22. electrical characteristics (1) 22.1 absolute maximum ratings* note: 1. electrical characteristics for this product have not yet been finalized. please consider all values listed herein as preliminary and non-contractual. operating temperature................................... -40c to +105c or operating temperature .............................. -40c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature...................................... -65c to +150c voltage on any pin except reset with respect to ground .................................-1.0v to v cc +0.5v voltage on reset with respect to ground ......-1.0v to +13.0v maximum operating voltage.............................................. 6.0v dc current per i/o pin.................................................. 40.0ma dc current v cc and gnd pins .............. ........... ......... 200.0ma 266 7734q?avr?02/12 at90pwm81/161 22.2 dc characteristics t a = -40c to +105c, v cc = 2.7v to 5.5v (unless otherwise noted). symbol parameter condition mi nimum typical maximum units v il input low voltage port b & d and xtal1, xtal2 pins as i/o -0.5 0.2v cc (1) v v ih input high voltage port b d and xtal1, xtal2 pins as i/o 0.6v cc (2) v cc +0.5 v il1 input low voltage xtal1 pin , external clock selected -0.5 0.1v cc (1) v ih1 input high voltage xtal1 pin , external clock selected 0.7v cc (2) v cc +0.5 v il2 input low voltage reset pin -0.5 0.2v cc (1) v ih2 input high voltage reset pin 0.9v cc (2) v cc +0.5 v il3 input low voltage reset pin as i/o -0.5 0.2v cc (1) v ih3 input high voltage reset pin as i/o 0.8v cc (2) v cc +0.5 v ol output low voltage (3) (port b & d and xtal1, xtal2 pins as i/o) i ol = 10ma, v cc = 5v i ol = 5ma, v cc = 3v 0.6 0.5 v oh output high voltage (4) (port b & d and xtal1, xtal2 pins as i/o) i oh = -10ma, v cc = 5v i oh = -5ma, v cc = 3v 4.3 2.5 v ol3 output low voltage (3) (reset pin as i/o) i ol = 2.1ma, v cc = 5v i ol = 0.8ma, v cc = 3v 0.7 0.5 v oh3 output high voltage (4) (reset pin as i/o) i oh = -0.6ma, v cc = 5v i oh = -0.4ma, v cc = 3v 3.8 2.2 i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1 r rst reset pull-up resistor 30 200 kw r pu i/o pin pull-up resistor 20 50 267 7734q?avr?02/12 at90pwm81/161 i cc power supply current active 8mhz, v cc = 3v, rc osc., prr = 0xff 3.5 5 ma active 16mhz, v cc = 5v, ext clock, prr = 0xff 10.5 15 idle 8mhz, v cc = 3v, rc osc 1.5 2 idle 16mhz, v cc = 5v, ext clock 4.5 7 power-down mode (5) wdt enabled,v cc = 3v 25c 7a wdt enabled, v cc = 3v 105c 30 wdt enabled, v cc = 5v 25c 10 a wdt enabled, v cc = 5v 105c 50 wdt disabled, v cc = 3v 25c 0.5 a wdt disabled, v cc = 3v 105c 25 wdt disabled, v cc = 5v 25c 1 wdt disabled, v cc = 5v 105c 40 a v ref internal voltage reference (7) @25c 2.46 2.56 2.66 v analog comparator input common mode range 0.1 v cc - 0.1 input offset voltage 0.1 269 7734q?avr?02/12 at90pwm81/161 note: 1. ?maximum? means the highest value where the pin is guaranteed to be read as low. 2. ?minimum? means the lowest value where the pin is guaranteed to be read as high. 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: so20 and tqfn package: 1] the sum of all i ol , for all ports, should not exceed 400ma. 2] the sum of all i ol , for ports b6 - b7, d0 - d3, e0 should not exceed 100ma. 3] the sum of all i ol , for ports b0 - b1, d4, e1 - e2 should not exceed 100ma. i cc power supply current active 8mhz, v cc = 3v, rc osc, prr = 0xff 3.5 5 ma active 16mhz, v cc = 5v, ext clock, prr = 0xff 10.5 15 idle 8mhz, v cc = 3v, rc osc 1.5 2 idle 16mhz, v cc = 5v, ext clock 4.5 7 power-down mode (5) wdt enabled, v cc = 3v 25c 7 a wdt enabled, v cc = 3v 125c 70 wdt enabled, v cc = 5v 25c 10 wdt enabled, v cc = 5v 125c 110 wdt disabled, v cc = 3v 25c 0.5 wdt disabled, v cc = 3v 125c 35 wdt disabled, v cc = 5v 25c 1 wdt disabled, v cc = 5v 125c 55 v ref internal voltage reference (7) @25c 2.46 2.56 2.66 v analog comparator input common mode range 0.1 v cc - 0.1 input offset voltage 0.1 271 7734q?avr?02/12 at90pwm81/161 22.3.4 external clock drive 22.4 maximum speed vs. v cc maximum frequency is depending on v cc. as shown in figure 22-2 on page 271 , the maximum frequency equals 12mhz when v cc is contained between 2.7v and 4.5v and equals 16mhz when v cc is contained between 4.5v and 5.5v. figure 22-2. maximum frequency vs. v cc , at90pwm81/161. 22.5 pll characteristics table 22-3. external clock drive. symbol parameter v cc = 2.7v - 5.5v v cc = 4.5v - 5.5v units minimum maximum minimum maximum 1/t clcl oscillator frequency 0 12 0 16 mhz t clcl clock period 83 62 ns t chcx high time 30 20 t clcx low time 30 20 t clch rise time 1.6 0.5 ms t chcl fall time 1.6 0.5 d t clcl change in period from one clock cycle to the next 22% safe operating area 16mhz 8mhz 2.7v 5.5v 4.5v 12mhz table 22-4. pll characteristics - v cc = 2.7v to 5.5v (unless otherwise noted). symbol parameter minimum typical maximum units pll if input frequency (1) 8mhz pll f pll factor 4 8 (2) pll lt lock-in time 64 s 272 7734q?avr?02/12 at90pwm81/161 notes: 1. while connected to external clock or extern al oscillator, pll input frequency must be selected to provide outputs with frequency in accordance with driven parts of the circuit. 2. when v cc is below 4.5v, maximum pll f is 6. 22.6 spi timing characteristics see figure 22-3 on page 273 and figure 22-4 on page 273 for details. notes: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck <12mhz - 3 t clcl for f ck >12mhz table 22-5. spi timing parameters. description mode minimum typical maximum units 1 sck period master see table 14- 5 on page 187 ns 2 sck high/low ma ster 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck ns 12 rise/fall time slave 1.6 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck 273 7734q?avr?02/12 at90pwm81/161 figure 22-3. spi interface timing requirements (master mode). figure 22-4. spi interface timing requirements (slave mode). mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 6 1 22 3 4 5 8 7 mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 1 7 1 5 9 x 1 6 274 7734q?avr?02/12 at90pwm81/161 22.7 adc characteristics table 22-6. adc characteristics - t a = -45 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted). symbol parameter condition minimum typical maximum units resolution single ended conversion 10 bits differential conversion, gain = 5 or 10 8 differential conversion, gain = 20 or 40 8 absolute accuracy single ended conversion, v cc = 4v, v ref = 4v adc clock = 1mhz 24 lsb single ended conversion, v cc = 2.7v, v ref =2.56v adc clock = 2mhz 2.2 4 differential conversion, gain = 5 or 10 v cc = 5v, v ref = 4v adc clock = 1mhz 1.2 2.0 differential conversion, gain = 20 or 40 v cc = 5v, v ref = 4v adc clock = 2mhz 1.5 3.0 integral non-linearity single ended conversion, v cc = 4v, v ref = 4v adc clock = 1mhz 0.6 1 lsb single ended conversion, v cc = 4v, v ref = 4v adc clock = 2mhz 0.8 1.5 single ended conversion, v cc = 2.7v, v ref = 2.56v adc clock = 2mhz 1.0 2.5 differential conversion, gain=5 or 10 v cc = 5v, v ref = 4v adc clock = 1mhz 0.5 1.0 differential conversion, gain=20 or 40 v cc = 5v, v ref = 4v adc clock = 2mhz 0.8 2.0 275 7734q?avr?02/12 at90pwm81/161 differential non-linearity single ended conversion, v cc = 4v, v ref = 4v adc clock = 1mhz 0.2 0.5 lsb single ended conversion, v cc = 4v, v ref = 4v adc clock = 2mhz 0.6 1 single ended conversion, v cc = 2.7v, v ref =2.56v adc clock = 2mhz 1.0 2.5 differential conversion, gain=5 or 10 v cc = 5v, v ref = 4v adc clock = 1mhz 0.3 0.8 differential conversion, gain=20 or 40 v cc = 5v, v ref = 4v adc clock = 2mhz 0.5 1.0 gain error single ended conversion, v cc = 4v, v ref = 4v adc clock = 1mhz 0.0 -6.0 lsb single ended conversion, v cc = 2.7v, v ref = 2.56v adc clock = 2mhz 0.0 -6.0 differential conversion, v cc = 5v, v ref = 4v adc clock = 1mhz -2.0 +2.0 offset error single ended conversion, v cc = 4v, v ref = 4v adc clock = 1mhz -1.0 2.0 lsb single ended conversion, v cc = 2.7v, v ref = 2.56v adc clock = 2mhz 1.0 4.0 differential conversion, v cc = 5v, v ref = 4v adc clock = 1mhz -1.0 +1.0 conversion time single conversion 8 260 s clock frequency 50 2000 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 2.56 av cc - 0.6 v v in input voltage single ended conversion gnd v ref differential conversion -v ref /gain +v ref /gain input bandwidth single ended conversion 38.5 khz differential conversion 4 table 22-6. adc characteristics - t a = -45 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted). (continued) symbol parameter condition minimum typical maximum units 276 7734q?avr?02/12 at90pwm81/161 22.8 dac characteristics 22.9 parallel programmi ng characteristics figure 22-5. parallel programming timing, including some general timing requirements. r ref reference input resistance 30 kw r ain analog input resistance 23 c ain analog input capacitor 10 pf i hsm increased current consumption high speed mode single ended conversion 380 a table 22-7. dac characteristics - t a = -45c to +105c, v cc = 2.7v to 5.5v (unless otherwise noted). symbol parameter condition minimum typical maximum units resolution dac 10 absolute accuracy v cc = 4v, v ref = 4v 2.5 5 lsb integral non-linearity v cc = 4v, v ref = 4v 0.8 1.5 differential non-linearity v cc = 4v, v ref = 4v 0.2 0.5 gain error v cc = 4v, v ref = 4v -5.0 0.0 offset error v cc = 4v, v ref = 4v 0.0 2.0 v ref reference voltage 2.56 av cc v table 22-6. adc characteristics - t a = -45 c to +105 c, v cc = 2.7v to 5.5v (unless otherwise noted). (continued) symbol parameter condition minimum typical maximum units data & contol (data , xa0 , xa1/bs2 , pagel/bs1) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rd y /bs y t plbx t bvph t xlwl t wlbx t bvwl wlrl 277 7734q?avr?02/12 at90pwm81/161 figure 22-6. parallel programming timing, loading sequence with timing requirements (1) . note: 1. the timing requirements shown in figure 22-5 on page 276 (that is, t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 22-7. parallel programming timing, reading sequence (within the same page) with timing requirements (1) . note: 1. the timing requirements shown in figure 22-5 on page 276 (that is, t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 xlxh t addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low b y te) load data (low b y te) load data (high b y te) load address (low b y te) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low b y te) read data (low b y te) read data (high b y te) load address (low b y te) t bvdv t oldv t xlol t ohd z 278 7734q?avr?02/12 at90pwm81/161 notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 22-8. parallel programming characteristics, v cc = 5v 10%. symbol parameter minimum typical maximum units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 ma t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 t xhxl xtal1 pulse width high 150 t xldx data and control hold after xtal1 low 67 t xlwl xtal1 low to wr low 0 t xlph xtal1 low to pagel high 0 t plxh pagel low to xtal1 high 150 t bvph bs1 valid before pagel high 67 t phpl pagel pulse width high 150 t plbx bs1 hold after pagel low 67 t wlbx bs2/1 hold after wr low 67 t plwl pagel low to wr low 67 t bvwl bs1 valid to wr low 67 t wlwh wr pulse width low 150 t wlrl wr low to rdy/bsy low 0 1 ms t wlrh wr low to rdy/bsy high (1) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 10 t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 t oldv oe low to data valid 250 t ohdz oe high to data tri-stated 250 279 7734q?avr?02/12 at90pwm81/161 23. at90pwm81/161 typi cal characteristics the following charts show typical behavior. t hese figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr register set and thus, the corresponding i/o modules are turned off. also the analog comparator is dis- abled during these measurements. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient tempera- ture. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l v cc f, where: c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential cur- rent drawn by the watchdog timer. 280 7734q?avr?02/12 at90pwm81/161 23.1 active supply current figure 23-1. active supply current vs. frequency (0.1mhz - 1.0mhz). active supply current vs. low frequency 5.5v 5.0v 4.5v 4.0v 3.6v 3.3v 2.7v 0 0.2 0.4 0.6 0.8 1 1.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 i cc [ma] 281 7734q?avr?02/12 at90pwm81/161 figure 23-2. active supply current vs. frequency (1mhz - 16mhz). figure 23-3. active supply current vs. v cc (internal rc o scillator, 8mhz). active supply current vs. frequency 5.5v 5.0v 4.5v 4.0v 3.6v 3.3v 2.7v 0 2 4 6 8 10 12 14 13579111315 frequency [mhz] i cc [ma] t e m p l a t e t o b e c h a r a c t e r i z e d active supply current vs. v cc internal rc oscillator, 8mhz 125c 105c 25c -40c 0 1 2 3 4 5 6 7 8 9 10 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [ma] 282 7734q?avr?02/12 at90pwm81/161 figure 23-4. active supply current vs. v cc (external clock, 16mhz). 23.2 idle supply current figure 23-5. idle supply current vs. frequency (0.1mhz - 1.0mhz). active supply current vs. v cc external clock 16mhz - atd on 125c 105c 25c -40c 0 2 4 6 8 10 12 14 16 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [ma] idle supply current vs. low frequency 5.5v 5.0v 4.5v 4.0v 3.6v 3.3v 2.7v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency [mhz] i cc [ma] 283 7734q?avr?02/12 at90pwm81/161 figure 23-6. idle supply current vs. frequency (1mhz - 16mhz). figure 23-7. idle supply current vs. v cc (internal rc o scillator, 8mhz). idle supply current vs. frequency 5.5v 5.0v 4.5v 4.0v 3.6v 3.3v 2.7v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 13579111315 frequency [mhz] i cc [ma] idle supply current vs. v cc internal rc oscillator, 8mhz 125c 105c 25c -40c 0 0.5 1 1.5 2 2.5 3 3.5 4 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [ma] 284 7734q?avr?02/12 at90pwm81/161 figure 23-8. idle supply current vs. v cc (external clock, 16mhz). 23.3 power-down supply current figure 23-9. power-down supply current vs. v cc (watchdog timer disabled). idle supply current vs. v cc external clock 16mhz 125c 105c 25c -40c 0 1 2 3 4 5 6 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [ma] power-down supply current vs. v cc watchdog timer disabled 125c 105c 25c -40c 0 2 4 6 8 10 12 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [a] 285 7734q?avr?02/12 at90pwm81/161 figure 23-10. power-down supply current vs. v cc (watchdog timer enabled). 23.4 pin pull-up figure 23-11. i/o pin pull-up resistor current vs. input voltage (v cc = 5v). power-down supply current vs. v cc watchdog timer enabled 125c 105c 25c -40c 0 5 10 15 20 25 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] i cc [a] t e m p l a t e t o b e c h a r a c t e r i z e d i/o pin pull-up resistor current vs. input voltage vcc = 5v 125c 105c 25c -40c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op [v] i op [a] 286 7734q?avr?02/12 at90pwm81/161 figure 23-12. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v). figure 23-13. i/o pin pull-up resistor current vs. input voltage, pe1 & pe2 pins (v cc = 5v). i/o pin pull-up resistor current vs. input voltage vcc = 2.7v 125c 105c 25c -40c 0 10 20 30 40 50 60 70 80 00.511.522.533.544.55 v op [v] i op [a] i/o pin pull-up resistor current vs. input voltage pe1 & pe2 pins vcc = 5v 125c 105c 25c -40c 0 20 40 60 80 100 120 140 160 00.511.522.533.544.55 v op [v] i op [a] 287 7734q?avr?02/12 at90pwm81/161 figure 23-14. i/o pin pull-up resistor current vs. input voltage, pe1 & pe2 pins (v cc = 2.7v). figure 23-15. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 5v). i/o pin pull-up resistor current vs. input voltage pe1 & pe2 pins vcc = 2.7v 125c 105c 25c -40c 0 10 20 30 40 50 60 70 80 90 00.511.522.533.544.55 v op [v] i op [a] reset pull-up resistor current vs. reset pin voltage vcc = 5v 125c 105c 25c -40c 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [a] 288 7734q?avr?02/12 at90pwm81/161 figure 23-16. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 2.7v). 23.5 pin output high voltage figure 23-17. i/o pin output voltage vs. source current (v cc = 5v). reset pull-up resistor current vs. reset pin voltage vcc = 2.7v 125c 105c 25c -40c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset [v] i reset [a] i/o pin output voltage vs. source current vcc = 5.0v 125c 105c 25c -40c 0 1 2 3 4 5 6 012345678910 i oh [ma] v oh [v] 289 7734q?avr?02/12 at90pwm81/161 figure 23-18. i/o pin output voltage vs. source current (v cc = 3v). 23.6 pin output low voltage figure 23-19. i/o pin output voltage vs. sink current (v cc = 5v). i/o pin output voltage vs. source current vcc = 3.0v 125c 105c 25c -40c 0 0.5 1 1.5 2 2.5 3 3.5 012345678910 i oh [ma] v oh [v] i/o pin output voltage vs. sink current vcc = 5.0v 125c 105c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 012345678910 i ol [ma] v ol [v] 290 7734q?avr?02/12 at90pwm81/161 figure 23-20. i/o pin output voltage vs. sink current (v cc = 3v). 23.7 pin thresholds figure 23-21. i/o pin input threshold voltage vs. v cc (vil, i/o pin read as '0'). i/o pin output voltage vs. sink current vcc = 3.0v 125c 105c 25c -40c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 012345678910 i ol [ma] v ol [v] i/o pin input threshold voltage vs. v cc vil, io pin read as '0' 125c 105c 25c -40c 0 0.5 1 1.5 2 2.5 3 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] threshold [v] 291 7734q?avr?02/12 at90pwm81/161 figure 23-22. i/o pin input threshold voltage vs. v cc (vih, i/o pin read as '1'). 23.8 bod thresholds figure 23-23. bod thresholds vs. temper ature (bodlevel is 4.3v). i/o pin input threshold voltage vs. v cc v ih, io pin rea d a s '1' 125c 105c 25c -40c 0 0.5 1 1.5 2 2.5 3 3.5 4 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] threshold [v] bod thresholds vs. temperature bodlevel is 4.3v rising vcc falling vcc 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature [c] threshold [v] 292 7734q?avr?02/12 at90pwm81/161 figure 23-24. bod thresholds vs. temper ature (bodlevel is 2.7v). 23.9 analog reference figure 23-25. v ref voltage vs. v cc . bod thresholds vs. temperature bodlevel is 2.7v rising vcc falling vcc 2.4 2.5 2.6 2.7 2.8 2.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature [c] threshold [v] iinternal vref vs vcc 125c 105c 25c -40c 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7 3.2 3.7 4.2 4.7 5.2 vcc (v) vref (v) 293 7734q?avr?02/12 at90pwm81/161 figure 23-26. v ref voltage vs. temperature. 23.10 internal oscillator speed figure 23-27. watchdog oscillato r frequency vs. v cc . internal vref vs temperature 5.5v 2.7v 2.35 2.4 2.45 2.5 2.55 2.6 2.65 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) aref (v) watc h d og osc il l ator fr equ en c y vs . oper atin g vol tage 125c 105c 25c -40c 0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14 2.7 3.2 3.7 4.2 4.7 5.2 v cc [v] f rc [mhz] 294 7734q?avr?02/12 at90pwm81/161 figure 23-28. calibrated 8mhz rc oscillator frequency vs. temperature. figure 23-29. calibrated 8mhz rc osc illator frequency vs. v cc . calibrated 8mhz rc oscillator frequency vs. temperature rc osc calibrated @ room temp 5.6v 5.4v 5.2v 5v 4v 2.8v 2.6v 7.7 7.8 7.9 8 8.1 8.2 8.3 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature [c] f rc [mhz] v calibrated 8mhz rc oscillator frequency vs. operating voltage rc osc calibrated @ room temp 125c 105c 25c -40c 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 2.4 2.9 3.4 3.9 4.4 4.9 5.4 v cc [v] f rc [mhz] 295 7734q?avr?02/12 at90pwm81/161 figure 23-30. calibrated 8mhz rc oscillator frequency vs. osccal value. 23.11 current consum ption in reset figure 23-31. reset supply current vs. v cc (0.1mhz - 1.0mhz, excluding current through the reset pull-up). int rc oscillator frequency vs. osccal 10000 cycles sampled with 250ns - vcc 3v 105c 25c -40c 400000 600000 800000 1000000 1200000 1400000 1600000 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal f rc reset supply current vs vcc excluding current through the reset pullup 5.5v 2.7v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency mhz all temperatures i cc (ma) 296 7734q?avr?02/12 at90pwm81/161 figure 23-32. reset supply current vs. v cc (1mhz - 16mhz, excluding current through the reset pull-up). 5.5v 2.7v 0 0.5 1 1.5 2 2.5 3 3.5 4 13579111315 frequency mhz all temperatures i cc (ma) 297 7734q?avr?02/12 at90pwm81/161 24. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) reserved ? ? ? ? ? ? ? ? (0xc5) reserved ? ? ? ? ? ? ? ? (0xc4) reserved ? ? ? ? ? ? ? ? (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) reserved ? ? ? ? ? ? ? ? (0xc1) reserved ? ? ? ? ? ? ? ? (0xc0) reserved ? ? ? ? ? ? ? ? 298 7734q?avr?02/12 at90pwm81/161 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) reserved ? ? ? ? ? ? ? ? (0xbc) reserved ? ? ? ? ? ? ? ? (0xbb) reserved ? ? ? ? ? ? ? ? (0xba) reserved ? ? ? ? ? ? ? ? (0xb9) reserved ? ? ? ? ? ? ? ? (0xb8) reserved ? ? ? ? ? ? ? ? (0xb7) reserved ? ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x9r) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 98 (0x8c) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 98 (0x8b) reserved ? ? ? ? ? ? ? ? (0x8a) tccr1b icnc1 ices1 ?wgm13 ? cs12 cs11 cs10 97 (0x89) eicra ? ? isc21 isc20 isc11 isc10 isc01 isc00 83 (0x88) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 39 (0x87) pllcsr - - pllf3 pllf2 pllf1 pllf0 plle plock 41 (0x86) prr prpsc2 ? prpscr prtim1 ? prspi ?pradc 49 (0x85) clkselr ? cout csut1 csut0 csel3 csel2 csel1 csel0 43 (0x84) clkcsr clkcce ? ? clkrdy clkc3 clkc2 clkc1 clkc0 42 (0x83) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 40 (0x82) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 59 (0x81) bgccr ? ? ? bgcc3 bgcc2 bgcc1 bgcc0 190 (0x80) bgcrr ? ? ? ? bgcr3 bgcr2 bgcr1 bgcr0 191 (0x7f) ac3con ac3en ac3ie ac3is1 ac3is0 ac3oea ac3m2 ac3m1 ac3m0 199 (0x7e) ac2con ac2en ac2ie ac2is1 ac2is0 ? ac2m2 ac2m1 ac2m0 198 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 299 7734q?avr?02/12 at90pwm81/161 (0x7d) ac1con ac1en ac1ie ac1is1 ac1is0 ? ac1m2 ac1m1 ac1m0 197 (0x7c) ac3econ ? ?ac3oiac3oe ? ac3h2 ac3h1 ac3h0 200 (0x7b) ac2econ ? ?ac2oiac2oe ? ac2h2 ac2h1 ac2h0 200 (0x7a) ac1econ ? ? ac1oi ac1oe ac1ice ac1h2 ac1h1 ac1h0 200 (0x79) amp0csr amp0en amp0is amp0g1 amp0g0 amp0gs ? amp0ts1 amp0ts0 225 (0x78) didr1 ? ? ? ? acmp1md amp0+d adc10d adc9d 222 (0x77) didr0 adc8d/acmp3d adc7d/amp0-d adc5d/acmp2d adc4d/acmp3m adc3d/acmpmd adc2d/acmp2m adc1d adc0d/acmp1d 222 (0x76) dacon daate dats2 dats1 dats0 ?dala ?daen 228 (0x75) room for analog test registers (0x74) (0x73) (0x72) (0x71) pasdly2 pasdly2[7:0] 139 (0x70) pcnfe2 pasdlkn2 pasdlkn1 pasdlkn0 pbfmn1 pelevna1 pelevnb1 pisel0a1 pisel0b1 137 (0x6f) pom2 pomv2b3 pomv2b2 pomv2b1 pomv2b0 pomv2a3 pomv2a2 pomv2a1 pomv2a0 142 (0x6e) psoc2 pos23 pos22 psync21 psync20 poen2d poen2b poen2c poen2a 134 (0x6d) picr2h pcst2 ? ? ? picr2[11:8] 142 (0x6c) picr2l picr2[7:0] 142 (0x6b) reserved ? ? ? ? ? ? ? ? (0x6a) psoc0 pisel0a1 pisel0b1 psync01 psync00 ?poen0b ?poen0a 171 (0x69) picr0h pcst0 ? ? ? picr0[11:8] 177 (0x68) picr0l picr0[7:0] 177 (0x67) pfrc2b pcae2b pisel2b pelev2b pflte2b prfm2b3 prfm2b2 prfm2b1 prfm2b0 141 (0x66) pfrc2a pcae2a pisel2a pelev2a pflte2a prfm2a3 prfm2a2 prfm2a1 prfm2a0 141 (0x65) ocr2sah ? ? ? ? ocr2sa[11:8] 135 (0x64) ocr2sal ocr2sa[7:0] 135 (0x63) pfrc0b pcae0b pisel0b pelev0b pflte0b prfm0b3 prfm0b2 prfm0b1 prfm0b0 175 (0x62) pfrc0a pcae0a pisel0a pelev0a pflte0a prfm0a3 prfm0a2 prfm0a1 prfm0a0 175 (0x61) ocr0sah ? ? ? ? ocr0sa[11:8] 172 (0x60) ocr0sal ocr0sa[7:0] 172 0x3f (0x5f) sreg ithsvnz c 10 0x3e (0x5e) sph ? ? ? ? sp11 sp10 sp9 sp8 12 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcnt18 98 0x3a (0x5a) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 98 0x39 (0x59) dach - / dac9 - / dac8 - / dac7 - / dac6 - / dac5 - / dac4 dac9 / dac3 dac8 / dac2 229 0x38 (0x58) dacl dac7 / dac1 dac6 /dac0 dac5 / - dac4 / - dac3 / - dac2 / - dac1 / - dac0 / 229 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 238 0x36 (0x56) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 188 0x35 (0x55) mcucr ? ? ? pud rstdis ckrc81 ivsel ivce 55 & 74 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 54 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 48 0x32 (0x52) msmcr monitor stop mode control register reserved 0x31 (0x51) dwdr dwdr[7:0] 232 0x30 (0x50) reserved ? ? ? ? ? ? ? ? 0x2f (0x4f) ocr2rah ? ? ? ? ocr2ra[11:8] 135 0x2e (0x4e) ocr2ral ocr2ra[7:0] 135 0x2d (0x4d) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc9 / adc3 adc8 / adc2 221 0x2c (0x4c) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / 221 0x2b (0x4b) ocr0rah ? ? ? ? ocr0ra[11:8] 172 0x2a (0x4a) ocr0ral ocr0ra[7:0] 172 0x29 (0x49) ocr2rbh ocr2rb[15:12] ocr2rb[11:8] 136 0x28 (0x48) ocr2rbl ocr2rb[7:0] 136 0x27 (0x47) ocr2sbh ? ? ? ? ocr2sb[11:8] 136 0x26 (0x46) ocr2sbl ocr2sb[7:0] 136 0x25 (0x45) ocr0rbh ocr0rb[15:12] ocr0rb[11:8] 172 0x24 (0x44) ocr0rbl ocr0rb[7:0] 172 0x23 (0x43) ocr0sbh ? ? ? ? ocr0sb[11:8] 172 0x22 (0x42) ocr0sbl ocr0sb[7:0] 172 0x21 (0x41) eimsk ? ? ? ? ? int2 int1 int0 84 0x20 (0x40) eifr ? ? ? ? ? intf2 intf1 intf0 84 0x1f (0x3f) eearh ? ? ? ? ? ? ?eear8 19 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 19 0x1d (0x3d) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 19 0x1c (0x3c) eecr nvmbsy eepage eepm1 eepm0 eerie eemwe eewe eere 19 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 300 7734q?avr?02/12 at90pwm81/161 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addre sses. the at90pwm81/161 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x 60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gpior20 26 0x1a (0x3a) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gpior10 26 0x19 (0x39) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gpior00 26 0x18 (0x38) spsr spif wcol ? ? ? ? ?spi2x 188 0x17 (0x37) spcr spie spe dord mstr cpol cpha spr1 spr0 186 0x16 (0x36) pctl2 ppre21 ppre20 pbf m2 paoc2b paoc2a parun2 pccyc2 prun2 140 0x15 (0x35) pcnf2 pfifty2 palock2 plo ck2 pmode21 pmode20 pop2 pclksel2 pome2 136 0x14 (0x34) pifr2 poac2b poac2a psei2 pev2b pev2a prn21 prn20 peop2 144 0x13 (0x33) pim2 - - pseie2 peve2b peve2a - peoepe2 peope2 143 0x12 (0x32) pctl0 ppre01 ppre00 pbfm01 paoc0b paoc0a pbfm00 pccyc0 prun0 174 0x11 (0x31) pcnf0 pfifty0 palock0 p lock0 pmode01 pmode00 pop0 pclksel0 ? 173 0x10 (0x30) pifr0 poac0b poac0a ? pev0b pev0a prn01 prn00 peop0 178 0x0f (0x2f) pim0 -- ? peve0b peve0a ? peoepe0 peope0 177 0x0e (0x2e) porte ? ? ? ? ? porte2 porte1 porte0 82 0x0d (0x2d) ddre ? ? ? ? ? dde2 dde1 dde0 82 0x0c (0x2c) pine ? ? ? ? ? pine2 pine1 pine0 82 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 82 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 82 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 82 0x08 (0x28) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 217 0x07 (0x27) adcsrb adhsm adncdis ? adssen adts3 adts2 adts1 adts0 220 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 219 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 81 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 82 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 82 0x02 (0x22) tifr1 ? ?icf1 ? ? ? ?tov1 99 0x01 (0x21) timsk1 ? ?icie1 ? ? ? ?toie1 99 0x00 (0x20) acsr ac3if ac2if ac1if ? ac3o ac2o ac1o ? 201 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 301 7734q?avr?02/12 at90pwm81/161 25. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd ? rd + rr z, c, n, v, h 1 adc rd, rr add with carry two registers rd ? rd + rr + c z, c, n, v, h 1 adiw rdl,k add immediate to word rdh: rdl ? rdh:rdl + k z, c, n, v, s 2 sub rd, rr subtract two registers rd ? rd - rr z, c, n, v, h 1 subi rd, k subtract constant from register rd ? rd - k z, c, n, v, h 1 sbc rd, rr subtract with carry two registers rd ? rd - rr - c z, c, n, v, h 1 sbci rd, k subtract with carry constant from reg. rd ? rd - k - c z, c, n, v, h 1 sbiw rdl,k subtract immediate from word rdh:rdl ? rdh:rdl - k z, c, n, v, s 2 and rd, rr logical and registers rd ? rd rr z, n, v 1 andi rd, k logical and register and constant rd ? rd k z, n, v 1 or rd, rr logical or registers rd ? rd v rr z, n, v 1 ori rd, k logical or register and constant rd ? rd v k z, n, v 1 eor rd, rr exclusive or registers rd ? rd ? rr z, n, v 1 com rd one?s complement rd ? 0xff - rd z, c, n, v 1 neg rd two?s complement rd ? 0x00 - rd z, c, n, v, h 1 sbr rd,k set bit(s) in register rd ? rd v k z, n, v 1 cbr rd,k clear bit(s) in register rd ? rd (0xff - k) z, n, v 1 inc rd increment rd ? rd + 1 z, n, v 1 dec rd decrement rd ? rd - 1 z, n, v 1 tst rd test for zero or minus rd ? rd rd z, n, v 1 clr rd clear register rd ? rd ? rd z, n, v 1 ser rd set register rd ? 0xff none 1 mul rd, rr multiply unsigned r1:r0 ? rd x rr z, c 2 muls rd, rr multiply signed r1:r0 ? rd x rr z, c 2 mulsu rd, rr multiply signed with unsigned r1:r0 ? rd x rr z, c 2 fmul rd, rr fractional multiply unsigned r1:r0 ? (rd x rr) << 1 z, c 2 fmuls rd, rr fractional multiply signed r1:r0 ? (rd x rr) << 1 z, c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? (rd x rr) << 1 z, c 2 branch instructions jmp (at90pwm161) kdirect jump pc ? knone3 call (at90pwm161) k direct call pc ? k none 4 rjmp k relative jump pc ? pc + k + 1 none 2 ijmp indirect jump to (z) pc ? z none 2 rcall k relative subroutine call pc ? pc + k + 1 none 3 icall indirect call to (z) pc ? z none 3 ret subroutine return pc ? stack none 4 reti interrupt return pc ? stack i 4 cpse rd,rr compare, skip if equal if (r d = rr) pc ? pc + 2 or 3 none 1/2/3 cp rd,rr compare rd - rr z, n, v, c, h 1 cpc rd,rr compare with carry rd - rr - c z, n, v, c, h 1 cpi rd,k compare register with immediate rd - k z, n, v, c, h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is se t if (rr(b)=1) pc ? pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleare d if (p(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is se t if (p(b)=1) pc ? pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc?pc+k + 1 none 1/2 brbc s, k branch if status flag cleared i f (sreg(s) = 0) then pc?pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1/2 brvs k branch if overflow flag is set i f (v = 1) then pc ? pc + k + 1 none 1/2 302 7734q?avr?02/12 at90pwm81/161 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) ? 1 none 2 cbi p,b clear bit in i/o register i/o(p,b) ? 0 none 2 lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z, c, n, v 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z, c, n, v 1 rol rd rotate left through carry rd(0)?c,rd(n+1)? rd(n),c?rd(7) z, c, n, v 1 ror rd rotate right through carry rd(7)?c,rd(n)? rd(n+1),c?rd(0) z, c, n, v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z, c, n, v 1 swap rd swap nibbles rd(3..0)?rd (7..4),rd(7..4)?rd(3..0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? t none 1 sec set carry c ? 1 c 1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1 n 1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1 z 1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1 i 1 cli global interrupt disable i ? 0 i 1 ses set signed test flag s ? 1 s 1 cls clear signed test flag s ? 0 s 1 sev set twos complement overflow. v ? 1 v 1 clv clear twos complement overflow v ? 0 v 1 set set t in sreg t ? 1 t 1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1 h 1 clh clear half carry flag in sreg h ? 0 h 1 data transfer instructions mov rd, rr move between registers rd ? rr none 1 movw rd, rr copy register word rd+1:rd ? rr+1:rr none 1 ldi rd, k load immediate rd ? k none 1 ld rd, x load indirect rd ? (x) none 2 ld rd, x+ load indirect and post-inc. rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-dec. x ? x - 1, rd ? (x) none 2 ld rd, y load indirect rd ? (y) none 2 ld rd, y+ load indirect and post-inc. rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-dec. y ? y - 1, rd ? (y) none 2 ldd rd,y+q load indirect with displacement rd ? (y + q) none 2 ld rd, z load indirect rd ? (z) none 2 ld rd, z+ load indirect and post-inc. rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-dec. z ? z - 1, rd ? (z) none 2 ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 lds rd, k load direct from sram rd ? (k) none 2 st x, rr store indirect (x) ? rr none 2 st x+, rr store indirect and post-inc. (x) ? rr, x ? x + 1 none 2 st - x, rr store indirect and pre-dec. x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 2 st y+, rr store indirect and post-inc. (y) ? rr, y ? y + 1 none 2 st - y, rr store indirect and pre-dec. y ? y - 1, (y) ? rr none 2 std y+q,rr store indirect with displacement (y + q) ? rr none 2 st z, rr store indirect (z) ? rr none 2 st z+, rr store indirect and post-inc. (z) ? rr, z ? z + 1 none 2 st -z, rr store indirect and pre-dec. z ? z - 1, (z) ? rr none 2 std z+q,rr store indirect with displacement (z + q) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 2 lpm load program memory r0 ? (z) none 3 lpm rd, z load program memory rd ? (z) none 3 lpm rd, z+ load program memory and post-inc rd ? (z), z ? z+1 none 3 spm store program memory (z) ? r1:r0 none - in rd, p in port rd ? p none 1 out p, rr out port p ? rr none 1 mnemonics operands description operation flags #clocks 303 7734q?avr?02/12 at90pwm81/161 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 304 7734q?avr?02/12 at90pwm81/161 26. ordering information note: all packages are pb free, fully lhf note: this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa tion and minimum quantities. note: parts numbers are for shipping in sticks (so) or in trays (q fn). thes devices can also be supplied in tape and reel. pleas e contact your local atmel sales office for detai led ordering information and minimum quantities. note: 1. marking on the package is pwm81-mn. 2. marking on the package is pwm81-mf. 3. marking on the package is pwm161-mn. 4. marking on the package is pwm161-mf. speed (mhz) power supply ordering code package operation range 16 2.7v - 5.5v at90pwm81-16me qfn32 (1) extended (-4 0c to 105c) at90pwm81-16se so20 at90pwm81-16mf qfn32 (2) extended (-4 0c to 125c) at90pwm81-16sf so20 16 2.7v - 5.5v at90pwm161-16mn qfn32 (3) extended (-4 0c to 105c) at90pwm161-16sn so20 at90pwm161-16mf qfn32 (4) extended (-4 0c to 125c) at90pwm161-16sf so20 package type so20 tg, 20-lead, 0.300? body width plastic gull wing small outline package (soic) qfn32 pn, 32-lead, 5.0 x 5.0mm body, 0.50mm pitch quad flat no lead package (qfn) 305 7734q?avr?02/12 at90pwm81/161 26.1 so20 306 7734q?avr?02/12 at90pwm81/161 26.2 qfn32 307 7734q?avr?02/12 at90pwm81/161 27. errata 27.1 errata at90pwm81 reva ? available on request 27.2 errata at90pwm81 revb ? clock switch disable ? crystal oscillator control with clock switch ? bod disable fuse ? psc output at reset ? flash and eeprom programming fail ure if cpu clock is switched ? adc amplifier measurement is unstable ? adc measurement reports abnormal values with psc2-synchronized conversions ? over-consumption in power down sleep mode 1. clock switch enable & disable after a ?enable clock source? or a ?disable clock source? command, the command is still active until the next access of clkcsr register. if clksel is written with a new value, the corresponding clock will be uninte ntionnaly enabled or disabled. work around: after the enable or disable command, write clkcsr with value 1< 309 7734q?avr?02/12 at90pwm81/161 1. clock switch enable & disable after a ?enable clock source? or a ?disable clock source? command, the command is still active until the next access of clkcsr register. if clksel is written with a new value, the corresponding clock will be uninte ntionnaly enabled or disabled. work around: atter the enable or disable command, write clkcsr with value 1< 315 7734q?avr?02/12 at90pwm81/161 28.6 rev. 7734f 1. clean chapter clock from all ?power save?. 2. update chapter ?ca librated inte rnal rc oscillator? on page 29. 3. update table 7-9 on page 35: sut for pll. 4. update chapter idle mode page 48. 5. update figure ?psc input module a? on page 119 and ?psc input module b? on page 120. 6. update figure ?psc behavior versus pscn input b in mode 14? on page 132. 7. update tables 14-16 ?psc edge & level input selection? on page 142 & 14-17 ?psc edge & level input selection? on page 142. 8. clean chaper psc (no more psc0 & psc1 register). 9. pscr registers and bits renamed from ?r? to ?0?. 10. update chapter ?digital input disable register 0 ? didr0? on page 207 & ?digital input disable register 1? didr1? on page 208. 11. update figures on parallel programming :figure 23-1 on page 261, figure 23-3 on page 265,figure 23-4 on page 266,figure 23-5 on page 268. 12. suppress chapter ?parallel programing characteristic? after section 23.7.14, now in ?parallel programming characteristics? on page 282. 28.7 rev. 7734g 1. update pin out definitions with pe3 as ar ef pin: figures ?20 pin packages? on page 4, ?32pin packages? on page 5,table ?pin out description? on page 7, chapter ?port e (p32..0) reset/ xtal1/ xtal2/aref? on page 8 and chapter ?alt ernate functions of port e? on page 82. 2. update table 7-1 on page 28 , for cksel 0111, 1100 & 1101. 3. update figure ?analog to digital converter block schematic? on page 210. 4. update table 19-3 on page 224; warning no more errata. 28.8 rev. 7734h 1. udate product configurationtable 2-1 on page 2. 2. add chapter ?rc oscillato r calibration? on page 31. 3. update chapter ?internal voltage reference? on page 58. 4. update chapter ?on chip voltage reference and temperature sensor overview? on page 192. 5. update chapter ?temperature measurement? on page 196. 6. update figure ?analog comparator block diagram? on page 201. 7. update chapter ?reading the signature row from software? on page 250. 8. update chapter ?calib rated internal rc oscilla tor accuracy? on page 277. 9. add chapter ?power consumption estimation with clock prescaling? on page 290. 10. update chapter ?errata? on page 325. 28.9 rev. 7734i 1. remove pe3 i/o function (only aref and adc functions) : pages 3, 4, 6, 7, 80, 81, 223. 2. remove the ?enable watchdog in automatic reload mode? page 34 and in table 6-12 on page 18. 3. update rc calibartion section 6.2.2.1 page 30. 4. remove chapter 6.3.7 on page 36. 316 7734q?avr?02/12 at90pwm81/161 5. remove chapter 16.3 band gap calibration procedure on page 191. 6. update temperature calibration on page 191. 7. remove chapter 16.4.3 two points temperature sensor calibration on page 197. 8. update signature row addressing on page249. 9. update dc characteristics : update table 23-1 page 275: rc calibartion @25c update table 23.2 page 272: -40c in place of -45c new table in 23.2: -40c to +125c 10. update erratasheet. 28.10 rev. 7734j 1. page 2 table 2-1: qfn32 : 32 pins. 2. page 6 table 3-2: so24 and qfn20 are removed. 3. page 30 section 6.2.2.1: rc osc. is monitored @125c. 4. page 51: table 8.2: bodenable is mandatory. 5. page 166: removed at90pwm2/3 comments. 6. page 267 table 23-1: user calibration at +5%. 7. page 271: update of adc characteristics. 8. page 273: add the dac characteristics. 28.11 rev. 7734k 1. page 193 16.4.1: removed the last sentence about reading of the temperature sensor during hot testing. 2. page 193 16.4.1: t formula modifed with new tsgain. 3. page 244 table 21.5: signature row adressing table updated with right address. 28.12 rev. 7734l 1. update errata rev e. 28.13 rev. 7734m 1. page 204: figure 18-1 removed refs2 bit. 2. .pages 277 to 294: update of typical characteristics. 28.14 rev. 7734n 1. page 52: update of bod levels. 2. pages 267, 268, 269, 270: update of vref, icc power-down, icc operating, icc idle and watchdog oscillator characteristics. 28.15 rev. 7734o 1. pages 275, 276 table 23-6: update of adc characteristics. 2. page 270: add a new line in table 23-1 (calibrated in ternal rc oscillator accuracy). 3. pages 267, 269, 279: update of analog comparator characteristics. 317 7734q?avr?02/12 at90pwm81/161 28.16 rev. 7734p 1. updated ?electrical characteristics (1)? on page 265 and ?at90pwm81/161 typical characteristics? on page 279 . 28.17 rev. 7734q 1. general update and countless, small corrections. 2. table 8-1 on page 62 has been updated. 3. the text in ?input mode operation? on page 160 has been updated. 4. changed the overlined text to normal text in the note below table 14-1 on page 182 . 5. removed the text/link ?13.9? from row #1 in table 13-5 on page 160 . 6. corrected figure text and figure for figure 17-15 on page 224 and figure 17-16 on page 224 . 7. the number ?2? below the list in ?reading the calibration byte? on page 260 has been removed. 8. new links have been added. 9. two places in table 21-16 on page 263 the text ?see table xxx on page xxx for details? has been replaced by ?see table 21-6 on page 251 for details?. 10. the text ?table 113? two places in table 4-4 on page 23 has been replaced by ? table 20-7 on page 246 ?. 11. in bit 4 ? pud: pull-up disable75 the text ?se? has been replaced by ?see ?configuring the pin? on page 69 for more details about this feature.? 12. in bit 5 ? icie1: timer/counter1, input capture interrupt enable on page 99 , the text ?xxx? has been replaced by ? table 8-1 on page 62 ?. 13. in ?input mode operation? on page 120 the text ?all? has been replaced by ?these modes are listed in table 12-7 ?. 14. the figure text in table 2-2 has been corrected to pin out description. 15. in the first sentence in ?interrupt handling? on page 131 the text ?(vector...)? has been removed. 16. in figure 13-2 on page 149 the text ?aralog? has been corrected to ?analog?. 17. in ?prescaling and conversion timing? on page 206 , section 6, the text ?(four xxx to be confirmed)? has been removed. 18. in ?adc conversion result? on page 215 the text ?table 82? has been replaced by ? table 17-2 on page 217 ?. 19. in table 22-4 on page 271 , note 1, the text ?(cpu core, psc... ? has been removed. 20. ?ordering information? on page 304 has been updated. 21. added at90pwm161 (16k flash, 1k sram) and updated the datasheet accordingly. 22. in chapter ?analog to digital converter? on page 47 the text ?cross reference moved? has been replaced by ? ?adc noise canceler? on page 210 ?. 23. in table 9-2 on page 74 the text ?figure? has been replaced by the cross reference ? figure 9- 5 on page 73 ?. 24. in chapter ?alternate port functions? on page 73 , just below table 9-2 on page 74 the cross reference table 9-2 has been added. 25. in chapter ?registers? on page 86 the text ?figure? has been replaced by the cross reference figure 11-1 two places. 26. in chapter ?psoc2 - psc 2 synchro and output configuration? on page 134 , in bullet point ?bit 3:0 ? prfmnx3:0: psc n fault mode?, page 141 , the text ?psc functional specification? has been replaced by ? table 12-7 on page 120 ?. 318 7734q?avr?02/12 at90pwm81/161 27. in chapter ?pfrc0b - pscr input b control register? on page 175 , in bullet point ?bit 3:0 ? prfm0x3:0: pscr fault mode?, page 176, the text ?pscr functional specification? has been replaced by ? table 13-5 on page 160 ?. 28. in ?bit 2, 1, 0? ac3m2, ac3m1, ac3m0: analog comparator 3 multiplexer register?, page 199 , the reference ?table 16-4? has been corrected to ? table 16-6 ?. 29. in table 21-5 on page 250 , the reference ?table 113? has been corrected to ? table 20-7 on page 246 ? two places. 30. in chapter ?signal names? on page 252 , the text ?in the following table? has been replaced by the reference ? table 21-8 on page 252 ?. 31. several cross references have been corrected. 32. the text ?the accuracy of this calibration is shown as factory calibration in table 24-1 on page 277? on page 30 has been changed into ?the accuracy of this calibration is shown as factory calibration in table 22-2 on page 270 ?. 33. the first note in bit 2? ckrc81: frequency select ion of the calibrated 8/1mhz rc oscillator on page 42 is corrected to this bit only can be changed only when the rc oscillator is enabled. 34. note 1 below figure 16-1 on page 195 is changed to ? refer to figure 2-1 on page 3 and figure 2-2 on page 4 for analog comparator pin placement.? 35. figure 16-2 on page 196 has been corrected. 36. in ?miso/acmp3/adc8? bit 6? on page 75 the ?ddb0? has been corrected to ?ddb6?, and the ?portb0? has been corrected to ?portb6?. 37. in ?adc5/acmp2/int1/sck ? bit 5? on page 76 the ?ddd4? has been corrected to ?ddb5?, and the ?port? has been corrected to ?portb5?. 38. in ?mosi/adc3/acmpm? bit 4? on page 76 the ?ddb1? has been corrected to ?ddb4?, and the ?portb1? has been corrected to ?portb4?. 39. missing information in table 9-4 on page 77 , table 9-5 on page 77 , table 9-7 on page 79 , table 9-8 on page 80 and table 9-10 on page 81 has been added. 40. paragraphs one and two in ?in-system reprogrammable flash program memory? on page 16 have been changed to to include more data regarding the at90pwm161. 41. the text ?tbd? in table 21-7 on page 251 has been changed into ?8b?. 42. the text in bullet point number three below table 21-7 on page 251 has been expanded to include the at90pwm161. 43. the text ?calibration accuracy? in the heading of table 22-2 on page 270 has been changed into ?accuracy?. 44. the text ?at90pwm161 reva? has been added to the heading in section 27.5 on page 311 . 45. jmp and call instructions are ad ded to ?branch instructions? in section 25. on page 301 . 46. ?errata at90pwm161 reva? on page 312 and ?errata at90pwm161 revb? on page 313 are added. 47. in ?errata at90pwm161 revb? on page 313 , and in ?errata at90pwm161 reva? on page 312 the pscrrb fuse is added. 48. in ?features? on page 227 the bullet points ?the dac could be connected to the negative inputs of the analog comparators and/or to a dedicated output driver? and ?output impedance around 1kohm? have been removed. 49. the text ?amp3d? has been replaced by ?acmp3d? in ?didr0 - digital input disable register 0? on page 202 , ?didr0 - digital input disable register 0? on page 222 , and ?register summary? on page 297 . 319 7734q?avr?02/12 at90pwm81/161 50. in ?features? on page 100 , the text in one of the bullet pints has been corrected to ?abnormality protection function, emergency input to force all outputs to low level?. 51. @25c has been removed several places in the table in ?dc characteristics? . 52. the rows describing 105c on page 269 in the table in ?dc characteristics? have been removed. 53. the values in table 7-2 on page 53 has been corrected. 54. the text below ?description? in table 13-8 on page 171 has been corrected. 55. the text below ?description? in table 13-9 on page 171 has been corrected. 56. a new feature has been added in section 18.1, page 227 . 57. the address for atmel japan has been changed. i 7734q?avr?02/12 at90pwm81/161 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 products configuration ...... .............. ............... .............. .............. ............ 2 2 pin configurations ..... ................ ................. ................ ................. ............ 3 2.1 pin descriptions .................................................................................................6 3 avr cpu core ................. ................ ................. .............. .............. ............ 8 3.1 introduction ........................................................................................................8 3.2 architectural overview .......................................................................................8 3.3 alu ? arithmetic logic unit ...............................................................................9 3.4 status register ................................................................................................10 3.5 general purpose register file ........................................................................11 3.6 stack pointer ...................................................................................................12 3.7 instruction execution timing ...........................................................................12 3.8 reset and interrupt handling ...........................................................................13 4 memories ............... .............. .............. ............... .............. .............. .......... 16 4.1 in-system reprogrammable flash program memory .....................................16 4.2 sram data memory ........................................................................................17 4.3 eeprom data memory . ................. ................ ............. ............ ............. ..........18 4.4 fuse bits ..........................................................................................................22 4.5 i/o memory ......................................................................................................26 4.6 general purpose i/o registers .......................................................................26 5 system clock and clock options ................ ................. .............. .......... 27 5.1 clock systems and their distribution ...............................................................27 5.2 clock sources .................................................................................................28 5.3 dynamic clock switch .....................................................................................35 5.4 system clock prescaler ..................................................................................39 5.5 register description ........................................................................................39 6 power management and sleep mo des ............... .............. ............ ........ 45 6.1 sleep modes ....................................................................................................45 6.2 idle mode .........................................................................................................45 6.3 adc noise reduction mode ............................................................................46 6.4 power-down mode ...........................................................................................46 6.5 standby mode .................................................................................................46 ii 7734q?avr?02/12 at90pwm81/161 6.6 power reduction register ...............................................................................46 6.7 minimizing power consumption ......................................................................47 6.8 register description .........................................................................................48 7 system control and reset ...... ................ ................. ................ ............. 50 7.1 system control overview .................................................................................50 7.2 system control registers .................................................................................54 7.3 internal voltage reference ..............................................................................55 7.4 watchdog timer ..............................................................................................56 8 interrupts ........ ................. ................ ................. .............. .............. .......... 62 8.1 interrupt vectors in at90pwm81/161 .............................................................62 9 i/o-ports ............... ................ .............. ............... .............. .............. .......... 68 9.1 introduction ......................................................................................................68 9.2 ports as general digital i/o .............................................................................69 9.3 alternate port functions ..................................................................................73 9.4 register description for i/o-ports ....................................................................81 10 external interrupts .......... ................ ................. .............. .............. .......... 83 11 reduced 16-bit timer/counter1 ............. ................. ................ ............. 85 11.1 overview ..........................................................................................................85 11.2 accessing 16-bit registers ..............................................................................87 11.3 timer/counter clock sources .........................................................................90 11.4 counter unit ....................................................................................................91 11.5 input capture unit ...........................................................................................92 11.6 modes of operation .........................................................................................94 11.7 timer/counter timing diagrams .....................................................................95 11.8 16-bit timer/counter register description ......................................................97 12 power stage controller ? (p scn) ................ .............. .............. ........... 100 12.1 features ........................................................................................................100 12.2 overview ........................................................................................................100 12.3 psc description ............................................................................................101 12.4 signal description ..........................................................................................103 12.5 functional description ...................................................................................104 12.6 update of values ...........................................................................................110 12.7 enhanced resolution ....................................................................................111 12.8 psc inputs ....................................................................................................114 iii 7734q?avr?02/12 at90pwm81/161 12.9 psc input mode 1: stop signal, jump to opposite dead-time and wait .....121 12.10 psc input mode 2: stop signal, execute opposite pulse and wait ..............122 12.11 psc input mode 3: stop signal, execute opposite pulse while fault active 123 12.12 psc input mode 4: deactivate outputs without changing timing ...................124 12.13 psc input mode 5: stop signal and insert dead-time ..................................124 12.14 psc input mode 6: stop signal, jump to opposite dead-time and wait .....125 12.15 psc input mode 7: halt psc and wait for software action ..........................125 12.16 psc input mode 8: edge retrigger psc .......................................................126 12.17 psc input mode 9: fixed frequency edge retrigger psc ...........................127 12.18 psc input mode 14: fixed frequency edge retrigger psc and deactivate out- put 128 12.19 psc2 outputs ................................................................................................129 12.20 analog synchronization .................................................................................131 12.21 interrupt handling ..........................................................................................131 12.22 psc synchronization .....................................................................................132 12.23 psc clock sources .......................................................................................133 12.24 interrupts .......................................................................................................134 12.25 psc register definition .................................................................................134 12.26 psc2 specific register .................................................................................142 13 reduced power stage contro ller ? (pscr) ............ ................ ........... 147 13.1 features ........................................................................................................147 13.2 overview ........................................................................................................147 13.3 pscr description .........................................................................................148 13.4 signal description ..........................................................................................149 13.5 functional description ...................................................................................151 13.6 update of values ...........................................................................................154 13.7 enhanced resolution ......................................................................................155 13.8 pscr inputs ..................................................................................................155 13.9 pscr input mode 1: stop signal, jump to opposite dead-time and wait ...161 13.10 pscr input mode 2: stop signal, execute opposite dead-time and wait ..162 13.11 pscr input mode 3: stop signal, execute opposite while fault active ........163 13.12 pscr input mode 4: deactivate outputs without changing timing ................164 13.13 pscr input mode 5: stop signal and insert dead-time ...............................164 13.14 pscr input mode 6: stop signal, jump to opposite dead-time and wait ...165 13.15 pscr input mode 7: halt pscr and wait for software action .....................165 13.16 pscr input mode 8: edge retrigger psc ....................................................166 iv 7734q?avr?02/12 at90pwm81/161 13.17 pscr input mode 9: fixed frequency edge retrigger psc ........................167 13.18 pscr input mode 14: fixed frequency edge retrigger pscr and deactivate output 168 13.19 analog synchronization .................................................................................169 13.20 interrupt handling ..........................................................................................169 13.21 psc clock sources .......................................................................................169 13.22 interrupts .......................................................................................................170 13.23 pscr register definition ..............................................................................171 14 serial peripheral interface ? spi: ............... ................ .............. ........... 180 14.1 features ........................................................................................................180 14.2 overview ........................................................................................................180 14.3 ss pin functionality ......................................................................................184 14.4 data modes ...................................................................................................185 14.5 spi registers ..................................................................................................186 15 voltage reference and temperature sensor .............. .............. ........ 189 15.1 features ........................................................................................................189 15.2 on chip voltage reference and temperature sensor overview ....................189 15.3 register description ......................................................................................190 15.4 temperature measurement ...........................................................................192 16 analog comparator .......... .............. .............. .............. .............. ........... 194 16.1 features ........................................................................................................194 16.2 overview ........................................................................................................194 16.3 shared pins between analog comparator and adc .....................................196 16.4 analog comparator register description ......................................................196 17 analog to digital converte r - adc .............. .............. .............. ........... 203 17.1 features ........................................................................................................203 17.2 operation .......................................................................................................205 17.3 starting a conversion ....................................................................................205 17.4 prescaling and conversion timing ................................................................206 17.5 changing channel or reference selection ...................................................209 17.6 adc noise canceler .....................................................................................210 17.7 adc conversion result .................................................................................215 17.8 adc register description ..............................................................................217 17.9 amplifier .........................................................................................................222 17.10 amplifier control registers ............................................................................225 v 7734q?avr?02/12 at90pwm81/161 18 digital to analog converter - dac ....... ................. ................ ............. 227 18.1 features ........................................................................................................227 18.2 operation .......................................................................................................228 18.3 starting a conversion ....................................................................................228 18.4 dac register description ..............................................................................228 19 debugwire on-chip debug s ystem .............. .............. .............. ........ 231 19.1 features ........................................................................................................231 19.2 overview ........................................................................................................231 19.3 physical interface ..........................................................................................231 19.4 software break points ...................................................................................232 19.5 limitations of debugwire .............................................................................232 19.6 debugwire related register in i/o memory ................................................232 20 boot loader support ? read-while-wri te self-programming ......... 233 20.1 boot loader features ....................................................................................233 20.2 application and boot loader flash sections .................................................233 20.3 read-while-write and no read-while-write flash sections ........................233 20.4 boot loader lock bits ...................................................................................236 20.5 entering the boot loader program ................................................................237 20.6 addressing the flash during self-programming ...........................................239 20.7 self-programming the flash ..........................................................................240 21 memory programming ........ .............. ............... .............. .............. ........ 248 21.1 program and data memory lock bits ...........................................................248 21.2 fuse bits ........................................................................................................249 21.3 signature bytes .............................................................................................251 21.4 calibration byte .............................................................................................252 21.5 parallel programming parameters, pin mapping, and commands ...............252 21.6 serial programming pin mapping ..................................................................254 21.7 parallel programming ....................................................................................254 21.8 serial downloading ........................................................................................261 22 electrical characteristics (1) ............................................................................................... 265 22.1 absolute maximum ratings* .........................................................................265 22.2 dc characteristics .........................................................................................266 22.3 clock drive characteristics ...........................................................................270 22.4 maximum speed vs. v cc .................................................................................................................... 271 22.5 pll characteristics .......................................................................................271 vi 7734q?avr?02/12 at90pwm81/161 22.6 spi timing characteristics ............................................................................272 22.7 adc characteristics ......................................................................................274 22.8 dac characteristics ......................................................................................276 22.9 parallel programming characteristics ...........................................................276 23 at90pwm81/161 typical c haracteristics ............... ................ ........... 279 23.1 active supply current ....................................................................................280 23.2 idle supply current ........................................................................................282 23.3 power-down supply current .........................................................................284 23.4 pin pull-up .....................................................................................................285 23.5 pin output high voltage ..................................................................................288 23.6 pin output low voltage ...................................................................................289 23.7 pin thresholds ...............................................................................................290 23.8 bod thresholds ............................................................................................291 23.9 analog reference ..........................................................................................292 23.10 internal oscillator speed ...............................................................................293 23.11 current consumption in reset ......................................................................295 24 register summary ........... .............. .............. .............. .............. ........... 297 25 instruction set summary ... .............. ............... .............. .............. ........ 301 26 ordering information .......... .............. ............... .............. .............. ........ 304 26.1 so20 .............................................................................................................305 26.2 qfn32 ...........................................................................................................306 27 errata ........... ................ ................ ................. ................ .............. ........... 307 27.1 errata at90pwm81 reva ..............................................................................307 27.2 errata at90pwm81 revb ..............................................................................307 27.3 errata at90pwm81 revc ..............................................................................308 27.4 errata at90pwm81 revd ..............................................................................310 27.5 errata at90pwm81 reve ..............................................................................311 27.6 errata at90pwm161 reva ............................................................................312 27.7 errata at90pwm161 revb ............................................................................313 28 datasheet revision history for at90 pwm81/161 ........... .................. 314 28.1 rev. 7734a ....................................................................................................314 28.2 rev. 7734b ....................................................................................................314 28.3 rev. 7734c ....................................................................................................314 28.4 rev. 7734d ....................................................................................................314 vii 7734q?avr?02/12 at90pwm81/161 28.5 rev. 7734e ....................................................................................................314 28.6 rev. 7734f ....................................................................................................315 28.7 rev. 7734g ...................................................................................................315 28.8 rev. 7734h ....................................................................................................315 28.9 rev. 7734i .....................................................................................................315 28.10 rev. 7734j ....................................................................................................316 28.11 rev. 7734k ....................................................................................................316 28.12 rev. 7734l ....................................................................................................316 28.13 rev. 7734m ...................................................................................................316 28.14 rev. 7734n ....................................................................................................316 28.15 rev. 7734o ...................................................................................................316 28.16 rev. 7734p ....................................................................................................317 28.17 rev. 7734q ...................................................................................................317 table of contents ......... ................. ................ ................. ................ ........... i 7734q?avr?02/12 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaki shinagawa-ku tokyo 104-0032 japan tel : (+81) 3-6417-0300 fax : (+81) 3-6417-0370 ? 2012 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , avr logo ? , avr studio ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life. |
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